TESTING OF THE ELEFANT ASIC INTRODUCTION The testing program for the ELEFANT ASIC is divided into two parts. The first stage involves a small test bench, where only a limited number of devices will be tested to evaluate their performance. This is to verify that the design is indeed correct, and that the ASIC will meet the requirements. This testing applies to the prototypes and preproduction devices. In a second stage, a test system capable of testing all of the production chips will be designed. It has not be decided yet if the ASICs will be tested at LBL using a wafer probe station, or at an outside vendor. TEST PROCEDURE The test bench provides all the inputs required to setup and operate the chip and inject known stimuli. The normal data readout path is used to verify that the device behaves as expected. The important signals required to conduct the testing are listed below: Detector inputs: Selectable voltage functions on FADC analog inputs Selectable Strobes on TDC inputs Software programmable control lines: Selection bits: Event buffer select Channel select Output select Chip enable read*/Write Read control Data bits : Data bus Hardware control lines: Event number (from local counter) 15 MHz sampling clock (continuous) SYNC (reset) Trigger A) Functionality tests (not quantitative): 1) Digital logic integrity test: Set the ASIC in test mode. This writes the content of a counter into every RAM location of the chip. Read out all buffers and check data pattern. 1) Make sure each channel works: Load latency and event size at nominal values, Sync. DC level on every FADC channel Strobe on every TDC input Trigger Check that FADC/TDC data is present on all channels. 2) Inter channel short circuit test: DC level on one selected FADC input only Strobe on one selected TDC input only Trigger burst (4) Check that FADC/TDC data is present on one and only one channel. 3) Test channel selection: As test 2, but verify that the data is on the expected channel. 4) Test event buffer/ event number selection Compare event buffer select code with Trigger timer code and event number. Check for consistency 5) Test event size control (only one channel necessary) Put slow triangular pulse on FADC input Test with various event sizes. Check if FADC data is consistent with event size. 6) Test latency control Slow ramp on FADC. Test FADC first channel amplitude as a function of the latency. B) Quantitative tests: 1) TDC performance -linearity/missing codes Done dynamicaly. Timing strobes uncorrellated to the TDC clock are applied to the TDC inputs, and the TDC vernier codes are histogrammed. The linearity and missing code information is extracted from the histogram -timing resolution The "start " and "stop" pulses from a precision timing generator is applied to two TDC inputs, and the difference between the stop and start TDC code is histogrammed. The generator signals are uncorrellated to the TDC clock. The measurement is made with a set of known delays between the start and stop pulses. This test is sensitive to the truncation error, linearity error, and any delay jitter in the strobe paths. -frequency lock range The control voltage from the delay locked loop will be measured as a function of the clock frequency over a range suitable for acceptance. -cross talk effects Strobes from 2 random sources are applied to 2 TDC inputs. The difference histogram is plotted. Cross talk introduces structure in this histogram and can be detected qualitatively. 2) FADC performance -linearity/missing codes Done dynamicaly by histogramming the FADC codes generated with a triangular pulse shape at the input, covering the full FADC range. -noise A low amplitude triangular pulse (equivalent to 2 or 3 LSBs) is applied to the input, synchronous with the FADC clock. This is repeated a large number of times, and the sigma is calculated for each time bin. A global figure is then obtained from the average of the sigmas. -signal response a) A triangular pulse is applied to the input and compared to the expected function. b) A sine wave is applied to the input and the effective number of bits is calculated. -coupling to adjacent channels A pulse is applied to one input. The other channels are scanned for evidence of cross talk. TEST EQUIPMENT. For all of the digital tests, an HP pattern generator will provide stimulus to the chip, a Textronics Logic Analyzer will provide the readout of the chip, and the data will be read and reduced using LabView. The generation of analog inputs and the characterization of signals only available at internal probe points for the various tests will be done manualy, and the tests signals will be produced by various commercial generators (function, sine, precision timing, with ASCII or GPIB control). The digital testing sequence will be totally automated. A set of 21 different test vector sequences will need to be compared against the digital simulation. The TDC tests will require stepping a precise pulse delay through 1 ns increments. The TDC inputs use ATOM signal levels and will need logic translation. The FADC inputs are low level AC coupled analog signals and will need special signal generation and level translation, a DAC may be the most appropriate generation mechanism. Additional signals will be available at internal test points that can only be made available at a probe station. Up to 50 signals may need probing, and consideration will be given to the creation of a probe card for even the prototype tests. The production tests will definitely require a probe card and a GPIB controlled probe station if performed in house. The ELEFANT chip contains two new functional designs -- the digital receivers, and the analog receivers. These two new designs have a high risk associated with them and may need extensive testings. Both of these circuits will have separate test chippettes -- see the separate test plan for them.