J. P. Martin, Jul 19 1996 TESTING OF THE LBL ASIC INTRODUCTION The testing program for the ELEFANT ASIC is divided into two parts. The first stage involves a small test bench, where only a limited number of devices will be tested to evaluate their performance. This is to verify that the design is indeed correct, and that the ASIC will meet the requirements. This testing applies to the prototypes and preproduction devices. In a second stage, a test system capable of testing all of the production chips will be designed. It has not be decided yet if the ASICs will be tested before or after assembly in the readout subsystem. Assuming that the testing is done before, it will have to be conducted within a short time span starting approximately in Sept 97, when the production units are scheduled to be delivered, and completed quickly enough to be compatible with the commissioning of the preamplifier/readout subunits at the beginning of 98. The test bench would then need to have the capacity to test around 100 chips per week, including the burn in procedure. TEST PROCEDURE The following procedure is based on the very first design of the LBL ASIC, and may require minor accomodations for the newer design. The test bench provides all the inputs required to setup and operate the chip and inject known stimuli. The normal data readout path is used to verify that the device behaves as expected. The important signals required to conduct the testing are listed below: Detector inputs: Selectable voltage functions on FADC analog inputs Selectable Strobes on TDC inputs Software programmable control lines: Selection bits: Event buffer select Channel select Output select Chip enable read*/Write Read control Setup bits : Event size Latency Data bits : Data bus (bidirectional) Hardware control lines: Event number (from local counter) 15 MHz sampling clock (continuous) SYNC (reset) Trigger The testing procedure is divided into two test phases, and a burn in sequence. In a first pass, the devices are tested only for functionality. The devices that are not completely functional at this stage will be discarded without further testing or burn in. The other devices will then be submitted to burn in for 72 hours. Then, the devices will be submitted to the quantitative tests for the final approval. A) Functionality tests (not quantitative): 1) Digital logic integrity test: Set the ASIC in test mode. This writes the content of a counter into every RAM location of the chip. Read out all buffers and check data pattern. 1) Make sure each channel works: Load latency and event size at nominal values, Sync. DC level on every FADC channel Strobe on every TDC input Trigger Check that FADC/TDC data is present on all channels. 2) Inter channel short circuit test: DC level on one selected FADC input only Strobe on one selected TDC input only Trigger burst (4) Check that FADC/TDC data is present on one and only one channel. 3) Test channel selection: As test 2, but verify thet the data is on the expected channel. 4) Test event buffer/ event number selection Compare event buffer select code with Trigger timer code and event number. Check for consistency 5) Test event size control (only one channel necessary) Put slow triangular pulse on FADC input Test with various event sizes. Check if FADC data is consistent with event size. 6) Test latency control Slow ramp on FADC. Test FADC first channel amplitude as a function of the latency. B) Quantitative tests: 1) TDC performance -linearity/missing codes Done dynamicaly. Timing strobes uncorrellated to the TDC clock are applied to the TDC inputs, and the TDC vernier codes are histogrammed. The linearity and missing code information is extracted from the histogram -timing resolution The "start " and "stop" pulses from a precision timing generator is applied to two TDC inputs, and the difference between the stop and start TDC code is histogrammed. The generator signals are uncorrellated to the TDC clock. The measurement is made with a set of known delays between the start and stop pulses. This test is sensitive to the truncation error, linearity error, and any delay jitter in the strobe paths. -frequency lock range The control voltage from the delay locked loop will be measured as a function of the clock frequency over a range suitable for acceptance. -cross talk effects Strobes from 2 random sources are applied to 2 TDC inputs. The difference histogram is plotted. Cross talk introduces structure in this histogram and can be detected qualitatively. 2) FADC performance -linearity/missing codes Done dynamicaly by histogramming the FADC codes generated with a triangular pulse shape at the input, covering the full FADC range. -noise A low amplitude triangular pulse (equivalent to 2 or 3 LSBs) is applied to the input, synchronous with the FADC clock. This is repeated a large number of times, and the sigma is calculated for each time bin. A global figure is then obtained from the average of the sigmas. -signal response a) A triangular pulse is applied to the input and compared to the expected function. b) A sine wave is applied to the input and the effective number of bits is calculated. -coupling to adjacent channels A pulse is applied to one input. The other channels are scanned for evidence of cross talk. BURN IN: During the tests sequences, the circuit will be submitted to a few power on/ power down cycles, as well as a few thermal cycles. TEST EQUIPMENT. For the first set of tests, a custom readout and control modules will be built for the ELEFANT IC in VME format. The selection of inputs for the various tests will be done manualy, and the tests signals will be produced by various commercial generators (function, sine, precision timing, with ASCII or GPIB control). For the production tests, an extended version of the readout test card will be produced, including sofware controlled gates for the inputs. Approximately 16 of these cards would be constructed in VME format to test 16 or possibly 32 ASICS in parallel. A fanout system will also be required to distribute the generator signals to the 16 cards. The testing sequence will be totally automated. The burn in sequence will last 72 hours, and the burn in bench will accomodate 100 devices, with individual current limitation circuitry. The testing sequence will last for 24 hours, and accomodate 32 devices at a time. Assuming a 70% yield in the selection of the ASICs, 100 tested units could be delivered after 9 weeks of testing.