TESTING OF THE ELEFANT ASIC


INTRODUCTION

The testing program for the ELEFANT ASIC is divided into two parts. The
first stage  involves full characterization, where only a limited
number of devices will be tested to evaluate their performance. This is
to verify that the design is indeed correct, and that the ASIC will
meet the requirements. This testing applies to all three phases of the
design process, prototype, preproduction, and validation of the
production devices.

In the production testing, a test more limited system capable of
quickly testing all of the production chips will be used.  This system
will use the same facility for the characterization; however, there
will be no requirement for probing die and only full packaged
parts will be tested.

TEST PROCEDURE

The test bench provides all the inputs required to setup and operate
the chip and inject known stimuli. The normal data readout path is used
to verify that the device behaves as expected. The important signals
required to conduct the testing are listed below:


    Detector inputs: Selectable voltage functions on FADC analog inputs
                     Selectable Strobes on TDC inputs

    Software programmable control lines:
                     Selection bits: Event buffer select
                                     Channel select
                                     Output select
                                     Chip enable
                                     read*/Write
                                     Read control


                     Data bits     : Data bus 

    Hardware control lines:
                     Event number (from local counter)
                     15 MHz sampling clock (continuous)
                     SYNC (reset)
                     Trigger


A) Functionality tests (not quantitative):

1) Digital logic integrity test:
   Set the ASIC in test mode. This writes the content of a counter into every
   RAM location of the chip. Read out all buffers and check data pattern.
   
1) Verify that power cunsumption of chip is within limits.

2) Make sure each channel works:
   DC level on every FADC channel
   Strobe on every TDC input
   Trigger
          Check that FADC/TDC data is present on all channels.

3) Inter channel short circuit test:
   DC level on one selected FADC input only
   Strobe on one selected TDC input only
   Trigger burst (4)
          Check that FADC/TDC data is present on one and only one channel.

4) Test channel selection:
   As test 2, but verify that the data is on the expected channel.

5) Test event buffer/ event number selection
   Compare event buffer select code with Trigger timer code and event
   number. Check for consistency

6) Verify test mode test vectors.


B) Quantitative tests:

1) TDC performance  -linearity/missing codes
                     Done dynamicaly. Timing strobes correllated to the
		     TDC clock are applied in a sequence of increasing delay
                     to the TDC inputs, and the TDC
		     vernier codes are histogrammed. The linearity and missing 
		     code information is extracted from the histogram
		     
                    -frequency lock range
		    The control voltage from the delay locked loop will be
                    measured as a function of the clock frequency over a 
                    range suitable for acceptance.
		    

2) FADC performance 
                    -linearity/missing codes
                    Done dynamicaly by histogramming the FADC codes generated
		    with rectangular pulse shape at the input, covering the
		    full FADC range. 
		    		  		    
                    -coupling to adjacent channels
		    A pulse is applied to one input. The other channels are
		    scanned for evidence of cross talk.
		    

TEST EQUIPMENT.

For all of the digital tests, an HP pattern generator will provide stimulus to the chip,
an HP Logic Analyzer will provide the readout of the chip, and the data
will be read and reduced using IGOR software. The generation of analog inputs and
the characterization of signals only available at internal probe points for the
various tests will be done manualy, and the tests signals will be produced
by various commercial generators (function, precision timing, with
GPIB control). 
  
The digital testing sequence will be totally automated. A set of different
test vector sequences will need to be compared against the digital simulation.
The TDC tests will require stepping a precise pulse delay through 1 ns increments.
The TDC inputs use ATOM signal levels and will need logic translation.  The FADC
inputs are low level AC coupled analog signals and will need special signal
generation and level translation, a DAC may be the most appropriate generation
mechanism.  Additional signals will be available at internal test points that
can only be made available at a probe station.