From JPMARTIN@lps.umontreal.ca Mon Jul 29 15:33 PDT 1996 From: JPMARTIN@lps.umontreal.ca Date: Mon, 29 Jul 1996 18:34:02 -0400 (EDT) To: sakleinfelder@lbl.gov, i_kipnis@lbl.gov, HFWS2@slac.stanford.edu, genat@design.lbl.gov, GXH@slac.stanford.edu, lankford@lankford.ps.uci.edu, djn@slac.stanford.edu, coupal@slac.stanford.edu, melevi@lbl.gov, sfdow@lbl.gov Subject: Elefant chip committee report Content-Type: text Content-Length: 5135 Preliminary Design Review of the Elefant Digitizer IC 24 July 1996 LBNL J.F. Genat, I. Kipnis, S. Kleinfelder, J.P. Martin, H. Sadrozinski INTRODUCTION The BaBar Elefant digitizer integrated circuit is a complex chip with a high level of integration. The overall architecture of Elefant is sound and no fundamental problems are foreseen. However, the complexity of the full-scale chip, and possibility of problems integrating the many different blocks, should not be underestimated. TECHNICAL QUESTIONS The committee prepared a list of technical aspects that would require further study. This list is split into sub sections that correspond to the various functional blocks of the ASIC ANALOG RECEIVERS: - Perform Monte Carlo simulations to define bandwidth, accounting for the input characteristics of the FADC block - Optimize gain-bandwidth-power tradeoff. - Check linearity at full 3 Volts output. - Size of the analog receiver block (Layout) ? - ESD protection ? DIGITAL RECEIVERS: - Check temperature sensitivity (time walk) - Check power supply sensitivity - Test for jitter (after fabrication) TDC: - Check temperature and power supply sensitivity - Investigate recovery time of the delay locked loop after a sync that is changing the phase of the sampling clock - Verify that the absence of the clock does not damage the chip - Investigate the condition of the TDC in the absence of a clock after a RESET DRAM: - Verify that the DRAM will survive operating at high temperature after is has received some radiation damage. COMPLETE CHIP, and "vicinity": - The possibility of using at least a complementary CMOS output on the 8 output buffer lines should be evaluated in order to reduce EMI. - If the FPGA is built on a separate board, the possibility of putting the Elefant with the FPGA on this board could be studied. - On the control gate array, the run time control signals (e.g. "trigger", "clock", etc.) should also be complementary, even if the receiving end is single ended. - In general, the chip should not show a destructive behaviour or draw excessive current under any condition, such as the absence of a clock, power on, etc. TESTING The committee perceived the need to rethink the testing of the IC. The production testing and detailed characterization seems to be in good hands at U of Montreal, although the team should think through and plan careful the burn-in and testing sequence. The functional testing, on the other hand, could be a major time sink and be critical for the successful development of the IC. It has to be planned ahead of time, test-boards and set-ups have to be build and a test program has to be developed. This requires manpower, resident at LBL, with thourough understanding of the design and the design tools. Given the fact that part of the present group will leave this project in the Fall, new team members should be added asap to make them familiar with the IC project. CONCLUSION The committee commends the work the group has done so far. They have been careful in their design methodology and have, with good engineering sense, been building the Elefant chip block by block. In particular they have fabricated all the major subparts of the circuit and characterized them properly. The recommendations of the PDRR+CDR were also followed, regarding the analog dynamic range (with the possibility of bi-linear FADC), the trigger bits, the radiation hardness tests, the power dissipation. The electronic design options are also derived from thorough Monte-Carlo simulations at the detector cell level, giving confidence in the requirements. There was a perception in the committee of a lack of quality assurance in the verification process. The history of the project has shown insufficient attention to the details of the verification process. The committee strongly recommends that a formal design verification plan be developed up-front and strictly adhered to. Management of the project must ensure that all of the required actions have taken place in appropriate detail. In light of the quality verification process required, the amount of new design, simulation and layout still to be performed, the available manpower, and the many potential issues needed to be solved when integrating the full-scale prototype, the committee believes that a September submission date is very aggressive. We strongly recommend against skipping verification steps in order to meet the proposed submission date. We are worried that in the near future, the work will be carried out only by people with part time committement to this project. A realistic schedule should be drawn up which includes all the verification work before and testing after fabrication, and has as contingency a redesign and resubmit step. It should be compared to the overall drift chamber schedule.