*.TECH sce3m08hp * SPICE net list for CELL TDC64x8_S * // Led v5.7_1.1 Thu Oct 12 03:18:16 EDT 1995 Sun SPARC SunOS .SUBCKT Delay_tile_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 24 25 Mtp0 1 13 18 24 TP W=3.20U L=0.80U Mtn0 18 13 19 25 TN W=1.80U L=0.80U Mtn1 19 14 2 25 TN W=1.80U L=2.00U Mtp1 3 18 17 24 TP W=3.20U L=0.80U Mtn2 17 18 20 25 TN W=1.80U L=0.80U Mtn3 20 14 4 25 TN W=1.80U L=2.00U Mtp2 5 17 21 24 TP W=3.20U L=0.80U Mtn4 21 17 7 25 TN W=1.60U L=0.80U Mtp3 6 18 22 24 TP W=3.20U L=0.80U Mtn5 22 18 8 25 TN W=1.60U L=0.80U Mtp4 9 22 16 24 TP W=15.20U L=0.80U Mtn6 16 22 10 25 TN W=8.00U L=0.80U Mtp5 11 21 15 24 TP W=16.00U L=0.80U Mtn7 15 21 12 25 TN W=8.00U L=0.80U *.VDD vdd0 1 *.GND gnd0 2 *.VDD vdd1 3 *.GND gnd2 4 *.VDD vdd2 5 *.VDD vdd3 6 *.GND gnd1 7 *.GND gnd3 8 *.VDD vdd4 9 *.GND gnd5 10 *.VDD vdd5 11 *.GND gnd6 12 *.IN input 13 *.INOUT inout4 14 *.OUT Out_to_Dff 15 *.OUT Timing 16 *.OUT output1 17 *.OUT output2 17 *.INOUT inout5 14 *.Vnwell 24 0 5 *.Vbulk 23 0 0 *.Vpwell 25 0 0 *.Vbulk 23 0 5 *TEXT tp0 " "; *TEXT tn0 " "; *TEXT tn1 " "; *TEXT tp1 " "; *TEXT tn2 " "; *TEXT tn3 " "; *TEXT tp2 " "; *TEXT tn4 " "; *TEXT " "; *TEXT " "; *TEXT tp3 " "; *TEXT tn5 " "; *TEXT tp4 " "; *TEXT tn6 " "; *TEXT tp5 " "; *TEXT tn7 " "; *TEXT "Delay_tile"; .ENDS Delay_tile_S .SUBCKT Delay_Bal_S 1 2 3 4 5 6 7 11 12 Mtp0 1 3 8 11 TP W=3.20U L=0.80U Mtn0 8 3 9 12 TN W=1.80U L=0.80U Mtn1 9 4 2 12 TN W=1.80U L=2.00U Mtp1 7 8 5 11 TP W=11.20U L=0.80U Mtn2 5 8 6 12 TN W=6.00U L=0.80U *.VDD vdd0 1 *.GND gnd0 2 *.IN input 3 *.IN Delay_control 4 *.OUT Out_to_Phase 5 *.GND gnd1 6 *.VDD vdd1 7 *.INOUT control 4 *.Vnwell 11 0 5 *.Vbulk 10 0 0 *.Vpwell 12 0 0 *.Vbulk 10 0 5 *TEXT tp0 " "; *TEXT tn0 " "; *TEXT tn1 " "; *TEXT tp1 " "; *TEXT tn2 " "; *TEXT "Delay_Bal"; .ENDS Delay_Bal_S .SUBCKT Phase_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 36 + 37 Mtn0 24 4 1 37 TN W=2.00U L=0.80U Mtn1 25 3 24 37 TN W=2.00U L=0.80U Mtp0 26 3 25 36 TP W=4.00U L=0.80U Mtp1 2 4 26 36 TP W=4.00U L=0.80U Mtn2 27 25 6 37 TN W=4.00U L=0.80U Mtp3 5 25 27 36 TP W=8.00U L=0.80U Mtn3 28 4 7 37 TN W=2.40U L=0.80U Mtn4 29 25 28 37 TN W=2.40U L=0.80U Mtp6 8 30 31 36 TP W=4.00U L=0.80U Mtn5 31 30 29 37 TN W=2.40U L=0.80U Mtp2 9 25 31 36 TP W=4.00U L=0.80U Mtp4 10 4 31 36 TP W=4.00U L=0.80U Mtn6 32 30 11 37 TN W=2.00U L=0.80U Mtp8 12 4 33 36 TP W=12.00U L=0.80U Mtp5 33 27 34 36 TP W=12.00U L=0.80U Mtp7 34 30 32 36 TP W=12.00U L=0.80U Mtn7 32 27 13 37 TN W=2.00U L=0.80U Mtn8 32 4 14 37 TN W=2.00U L=0.80U Mtn9 30 3 16 37 TN W=4.00U L=0.80U Mtp10 15 3 30 36 TP W=8.00U L=0.80U Mtn10 23 32 18 37 TN W=2.00U L=4.00U Mtp11 17 31 23 36 TP W=2.00U L=2.00U Mtn11 19 23 19 37 TN W=30.00U L=350.00U Mtp9 20 23 20 36 TP W=30.00U L=350.00U Mtn12 21 22 23 37 TN W=8.00U L=0.80U *.GND gnd0 1 *.VDD vdd0 2 *.IN Phase_B 3 *.IN Phase_a 4 *.VDD vdd1 5 *.GND gnd1 6 *.GND gnd2 7 *.VDD vdd3 8 *.VDD vdd2 9 *.VDD vdd4 10 *.GND gnd3 11 *.VDD vdd5 12 *.GND gnd4 13 *.GND gnd5 14 *.VDD vdd6 15 *.GND gnd7 16 *.VDD vdd7 17 *.GND gnd8 18 *.GND gnd6 19 *.VDD vdd9 20 *.VDD vdd8 21 *.IN RESET 22 *.INOUT cap_volt 23 *.OUT Ph_Cntrl_L 23 *.OUT Ph_Cntrl_R 23 *.IN Phase_B_M1 3 *.Vnwell 36 0 5 *.Vbulk 35 0 0 *.Vpwell 37 0 0 *.Vbulk 35 0 5 *TEXT tn0 " "; *TEXT tn1 " "; *TEXT tp0 " "; *TEXT tp1 " "; *TEXT tn2 " "; *TEXT tp3 " "; *TEXT tn3 " "; *TEXT tn4 " "; *TEXT tp6 " "; *TEXT tn5 " "; *TEXT tp2 " "; *TEXT tp4 " "; *TEXT tn6 " "; *TEXT tp8 " "; *TEXT tp5 " "; *TEXT tp7 " "; *TEXT tn7 " "; *TEXT tn8 " "; *TEXT tn9 " "; *TEXT tp10 " "; *TEXT " "; *TEXT " "; *TEXT tn10 " "; *TEXT tp11 " "; *TEXT tn11 " "; *TEXT tp9 " "; *TEXT tn12 " "; *TEXT "Phase"; .ENDS Phase_S .SUBCKT Phi_Driver_S 1 2 3 4 5 6 7 9 10 Mtp4 3 7 6 9 TP W=20.00U L=0.80U Mtn4 6 7 1 10 TN W=8.00U L=0.80U Mtp5 4 6 5 9 TP W=40.00U L=0.80U Mtn6 5 6 2 10 TN W=16.00U L=0.80U *.GND gnd0 1 *.GND gnd1 2 *.VDD vdd3 3 *.VDD vdd4 4 *.OUT To_Channels 5 *.OUT To_Delay 6 *.IN PHI_in 7 *.Vnwell 9 0 5 *.Vbulk 8 0 0 *.Vpwell 10 0 0 *.Vbulk 8 0 5 *TEXT tp4 " "; *TEXT tn4 " "; *TEXT tp5 " "; *TEXT tn6 " "; *TEXT " "; *TEXT " "; *TEXT " "; *TEXT "Phi_Driver"; .ENDS Phi_Driver_S .SUBCKT DelayBuffer_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 + 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 + 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 + 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 + 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 1335 1336 XDelay_tile_S_i0 136 137 138 139 140 141 142 143 144 145 146 147 131 134 64 128 + 148 1335 1336 Delay_tile_S XDelay_tile_S_i1 149 150 151 152 153 154 155 156 157 158 159 160 148 134 63 127 + 161 1335 1336 Delay_tile_S XDelay_tile_S_i2 162 163 164 165 166 167 168 169 170 171 172 173 161 134 62 126 + 174 1335 1336 Delay_tile_S XDelay_tile_S_i3 175 176 177 178 179 180 181 182 183 184 185 186 174 134 61 125 + 187 1335 1336 Delay_tile_S XDelay_tile_S_i4 188 189 190 191 192 193 194 195 196 197 198 199 187 134 60 124 + 200 1335 1336 Delay_tile_S XDelay_tile_S_i5 201 202 203 204 205 206 207 208 209 210 211 212 200 134 59 123 + 213 1335 1336 Delay_tile_S XDelay_tile_S_i6 214 215 216 217 218 219 220 221 222 223 224 225 213 134 58 122 + 226 1335 1336 Delay_tile_S XDelay_tile_S_i7 227 228 229 230 231 232 233 234 235 236 237 238 226 134 57 121 + 239 1335 1336 Delay_tile_S XDelay_tile_S_i8 240 241 242 243 244 245 246 247 248 249 250 251 239 134 56 120 + 252 1335 1336 Delay_tile_S XDelay_tile_S_i9 253 254 255 256 257 258 259 260 261 262 263 264 252 134 55 119 + 265 1335 1336 Delay_tile_S XDelay_tile_S_i10 266 267 268 269 270 271 272 273 274 275 276 277 265 134 54 118 + 278 1335 1336 Delay_tile_S XDelay_tile_S_i11 279 280 281 282 283 284 285 286 287 288 289 290 278 134 53 117 + 291 1335 1336 Delay_tile_S XDelay_tile_S_i12 292 293 294 295 296 297 298 299 300 301 302 303 291 134 52 116 + 304 1335 1336 Delay_tile_S XDelay_tile_S_i13 305 306 307 308 309 310 311 312 313 314 315 316 304 134 51 115 + 317 1335 1336 Delay_tile_S XDelay_tile_S_i14 318 319 320 321 322 323 324 325 326 327 328 329 317 134 50 114 + 330 1335 1336 Delay_tile_S XDelay_tile_S_i15 331 332 333 334 335 336 337 338 339 340 341 342 330 134 49 113 + 343 1335 1336 Delay_tile_S XDelay_tile_S_i16 344 345 346 347 348 349 350 351 352 353 354 355 343 134 48 112 + 356 1335 1336 Delay_tile_S XDelay_tile_S_i17 357 358 359 360 361 362 363 364 365 366 367 368 356 134 47 111 + 369 1335 1336 Delay_tile_S XDelay_tile_S_i18 370 371 372 373 374 375 376 377 378 379 380 381 369 134 46 110 + 382 1335 1336 Delay_tile_S XDelay_tile_S_i19 383 384 385 386 387 388 389 390 391 392 393 394 382 134 45 109 + 395 1335 1336 Delay_tile_S XDelay_tile_S_i20 396 397 398 399 400 401 402 403 404 405 406 407 395 134 44 108 + 408 1335 1336 Delay_tile_S XDelay_tile_S_i21 409 410 411 412 413 414 415 416 417 418 419 420 408 134 43 107 + 421 1335 1336 Delay_tile_S XDelay_tile_S_i22 422 423 424 425 426 427 428 429 430 431 432 433 421 134 42 106 + 434 1335 1336 Delay_tile_S XDelay_tile_S_i23 435 436 437 438 439 440 441 442 443 444 445 446 434 134 41 105 + 447 1335 1336 Delay_tile_S XDelay_tile_S_i24 448 449 450 451 452 453 454 455 456 457 458 459 447 134 40 104 + 460 1335 1336 Delay_tile_S XDelay_tile_S_i25 461 462 463 464 465 466 467 468 469 470 471 472 460 134 39 103 + 473 1335 1336 Delay_tile_S XDelay_tile_S_i26 474 475 476 477 478 479 480 481 482 483 484 485 473 134 38 102 + 486 1335 1336 Delay_tile_S XDelay_tile_S_i27 487 488 489 490 491 492 493 494 495 496 497 498 486 134 37 101 + 499 1335 1336 Delay_tile_S XDelay_tile_S_i28 500 501 502 503 504 505 506 507 508 509 510 511 499 134 36 100 + 512 1335 1336 Delay_tile_S XDelay_tile_S_i29 513 514 515 516 517 518 519 520 521 522 523 524 512 134 35 99 + 525 1335 1336 Delay_tile_S XDelay_tile_S_i30 526 527 528 529 530 531 532 533 534 535 536 537 525 134 34 98 + 538 1335 1336 Delay_tile_S XDelay_tile_S_i31 539 540 541 542 543 544 545 546 547 548 549 550 538 134 33 97 + 551 1335 1336 Delay_tile_S XDelay_tile_S_i32 552 553 554 555 556 557 558 559 560 561 562 563 551 134 32 96 + 564 1335 1336 Delay_tile_S XDelay_tile_S_i33 565 566 567 568 569 570 571 572 573 574 575 576 564 134 31 95 + 577 1335 1336 Delay_tile_S XDelay_tile_S_i34 578 579 580 581 582 583 584 585 586 587 588 589 577 134 30 94 + 590 1335 1336 Delay_tile_S XDelay_tile_S_i35 591 592 593 594 595 596 597 598 599 600 601 602 590 134 29 93 + 603 1335 1336 Delay_tile_S XDelay_tile_S_i36 604 605 606 607 608 609 610 611 612 613 614 615 603 134 28 92 + 616 1335 1336 Delay_tile_S XDelay_tile_S_i37 617 618 619 620 621 622 623 624 625 626 627 628 616 134 27 91 + 629 1335 1336 Delay_tile_S XDelay_tile_S_i38 630 631 632 633 634 635 636 637 638 639 640 641 629 134 26 90 + 642 1335 1336 Delay_tile_S XDelay_tile_S_i39 643 644 645 646 647 648 649 650 651 652 653 654 642 134 25 89 + 655 1335 1336 Delay_tile_S XDelay_tile_S_i40 656 657 658 659 660 661 662 663 664 665 666 667 655 134 24 88 + 668 1335 1336 Delay_tile_S XDelay_tile_S_i41 669 670 671 672 673 674 675 676 677 678 679 680 668 134 23 87 + 681 1335 1336 Delay_tile_S XDelay_tile_S_i42 682 683 684 685 686 687 688 689 690 691 692 693 681 134 22 86 + 694 1335 1336 Delay_tile_S XDelay_tile_S_i43 695 696 697 698 699 700 701 702 703 704 705 706 694 134 21 85 + 707 1335 1336 Delay_tile_S XDelay_tile_S_i44 708 709 710 711 712 713 714 715 716 717 718 719 707 134 20 84 + 720 1335 1336 Delay_tile_S XDelay_tile_S_i45 721 722 723 724 725 726 727 728 729 730 731 732 720 134 19 83 + 733 1335 1336 Delay_tile_S XDelay_tile_S_i46 734 735 736 737 738 739 740 741 742 743 744 745 733 134 18 82 + 746 1335 1336 Delay_tile_S XDelay_tile_S_i47 747 748 749 750 751 752 753 754 755 756 757 758 746 134 17 81 + 759 1335 1336 Delay_tile_S XDelay_tile_S_i48 760 761 762 763 764 765 766 767 768 769 770 771 759 134 16 80 + 772 1335 1336 Delay_tile_S XDelay_tile_S_i49 773 774 775 776 777 778 779 780 781 782 783 784 772 134 15 79 + 785 1335 1336 Delay_tile_S XDelay_tile_S_i50 786 787 788 789 790 791 792 793 794 795 796 797 785 134 14 78 + 798 1335 1336 Delay_tile_S XDelay_tile_S_i51 799 800 801 802 803 804 805 806 807 808 809 810 798 134 13 77 + 811 1335 1336 Delay_tile_S XDelay_tile_S_i52 812 813 814 815 816 817 818 819 820 821 822 823 811 134 12 76 + 824 1335 1336 Delay_tile_S XDelay_tile_S_i53 825 826 827 828 829 830 831 832 833 834 835 836 824 134 11 75 + 837 1335 1336 Delay_tile_S XDelay_tile_S_i54 838 839 840 841 842 843 844 845 846 847 848 849 837 134 10 74 + 850 1335 1336 Delay_tile_S XDelay_tile_S_i55 851 852 853 854 855 856 857 858 859 860 861 862 850 134 9 73 + 863 1335 1336 Delay_tile_S XDelay_tile_S_i56 864 865 866 867 868 869 870 871 872 873 874 875 863 134 8 72 + 876 1335 1336 Delay_tile_S XDelay_tile_S_i57 877 878 879 880 881 882 883 884 885 886 887 888 876 134 7 71 + 889 1335 1336 Delay_tile_S XDelay_tile_S_i58 890 891 892 893 894 895 896 897 898 899 900 901 889 134 6 70 + 902 1335 1336 Delay_tile_S XDelay_tile_S_i59 903 904 905 906 907 908 909 910 911 912 913 914 902 134 5 69 + 915 1335 1336 Delay_tile_S XDelay_tile_S_i60 916 917 918 919 920 921 922 923 924 925 926 927 915 134 4 68 + 928 1335 1336 Delay_tile_S XDelay_tile_S_i61 929 930 931 932 933 934 935 936 937 938 939 940 928 134 3 67 + 941 1335 1336 Delay_tile_S XDelay_tile_S_i62 942 943 944 945 946 947 948 949 950 951 952 953 941 134 2 66 + 954 1335 1336 Delay_tile_S XDelay_tile_S_i63 955 956 957 958 959 960 961 962 963 964 965 966 954 134 1 65 + 967 1335 1336 Delay_tile_S XDelay_Bal_S_i0 968 969 131 134 132 970 971 1335 1336 Delay_Bal_S XDelay_Bal_S_i1 972 973 967 134 135 974 975 1335 1336 Delay_Bal_S XPhase_S_i0 976 977 135 132 978 979 980 981 982 983 984 985 986 987 988 989 990 + 991 992 993 994 133 134 1335 1336 Phase_S XPhi_Driver_S_i0 995 996 997 998 129 131 130 1335 1336 Phi_Driver_S *.OUT Out_to_Dff[63] 1 *.OUT Out_to_Dff[62] 2 *.OUT Out_to_Dff[61] 3 *.OUT Out_to_Dff[60] 4 *.OUT Out_to_Dff[59] 5 *.OUT Out_to_Dff[58] 6 *.OUT Out_to_Dff[57] 7 *.OUT Out_to_Dff[56] 8 *.OUT Out_to_Dff[55] 9 *.OUT Out_to_Dff[54] 10 *.OUT Out_to_Dff[53] 11 *.OUT Out_to_Dff[52] 12 *.OUT Out_to_Dff[51] 13 *.OUT Out_to_Dff[50] 14 *.OUT Out_to_Dff[49] 15 *.OUT Out_to_Dff[48] 16 *.OUT Out_to_Dff[47] 17 *.OUT Out_to_Dff[46] 18 *.OUT Out_to_Dff[45] 19 *.OUT Out_to_Dff[44] 20 *.OUT Out_to_Dff[43] 21 *.OUT Out_to_Dff[42] 22 *.OUT Out_to_Dff[41] 23 *.OUT Out_to_Dff[40] 24 *.OUT Out_to_Dff[39] 25 *.OUT Out_to_Dff[38] 26 *.OUT Out_to_Dff[37] 27 *.OUT Out_to_Dff[36] 28 *.OUT Out_to_Dff[35] 29 *.OUT Out_to_Dff[34] 30 *.OUT Out_to_Dff[33] 31 *.OUT Out_to_Dff[32] 32 *.OUT Out_to_Dff[31] 33 *.OUT Out_to_Dff[30] 34 *.OUT Out_to_Dff[29] 35 *.OUT Out_to_Dff[28] 36 *.OUT Out_to_Dff[27] 37 *.OUT Out_to_Dff[26] 38 *.OUT Out_to_Dff[25] 39 *.OUT Out_to_Dff[24] 40 *.OUT Out_to_Dff[23] 41 *.OUT Out_to_Dff[22] 42 *.OUT Out_to_Dff[21] 43 *.OUT Out_to_Dff[20] 44 *.OUT Out_to_Dff[19] 45 *.OUT Out_to_Dff[18] 46 *.OUT Out_to_Dff[17] 47 *.OUT Out_to_Dff[16] 48 *.OUT Out_to_Dff[15] 49 *.OUT Out_to_Dff[14] 50 *.OUT Out_to_Dff[13] 51 *.OUT Out_to_Dff[12] 52 *.OUT Out_to_Dff[11] 53 *.OUT Out_to_Dff[10] 54 *.OUT Out_to_Dff[9] 55 *.OUT Out_to_Dff[8] 56 *.OUT Out_to_Dff[7] 57 *.OUT Out_to_Dff[6] 58 *.OUT Out_to_Dff[5] 59 *.OUT Out_to_Dff[4] 60 *.OUT Out_to_Dff[3] 61 *.OUT Out_to_Dff[2] 62 *.OUT Out_to_Dff[1] 63 *.OUT Out_to_Dff[0] 64 *.OUT Timing[63] 65 *.OUT Timing[62] 66 *.OUT Timing[61] 67 *.OUT Timing[60] 68 *.OUT Timing[59] 69 *.OUT Timing[58] 70 *.OUT Timing[57] 71 *.OUT Timing[56] 72 *.OUT Timing[55] 73 *.OUT Timing[54] 74 *.OUT Timing[53] 75 *.OUT Timing[52] 76 *.OUT Timing[51] 77 *.OUT Timing[50] 78 *.OUT Timing[49] 79 *.OUT Timing[48] 80 *.OUT Timing[47] 81 *.OUT Timing[46] 82 *.OUT Timing[45] 83 *.OUT Timing[44] 84 *.OUT Timing[43] 85 *.OUT Timing[42] 86 *.OUT Timing[41] 87 *.OUT Timing[40] 88 *.OUT Timing[39] 89 *.OUT Timing[38] 90 *.OUT Timing[37] 91 *.OUT Timing[36] 92 *.OUT Timing[35] 93 *.OUT Timing[34] 94 *.OUT Timing[33] 95 *.OUT Timing[32] 96 *.OUT Timing[31] 97 *.OUT Timing[30] 98 *.OUT Timing[29] 99 *.OUT Timing[28] 100 *.OUT Timing[27] 101 *.OUT Timing[26] 102 *.OUT Timing[25] 103 *.OUT Timing[24] 104 *.OUT Timing[23] 105 *.OUT Timing[22] 106 *.OUT Timing[21] 107 *.OUT Timing[20] 108 *.OUT Timing[19] 109 *.OUT Timing[18] 110 *.OUT Timing[17] 111 *.OUT Timing[16] 112 *.OUT Timing[15] 113 *.OUT Timing[14] 114 *.OUT Timing[13] 115 *.OUT Timing[12] 116 *.OUT Timing[11] 117 *.OUT Timing[10] 118 *.OUT Timing[9] 119 *.OUT Timing[8] 120 *.OUT Timing[7] 121 *.OUT Timing[6] 122 *.OUT Timing[5] 123 *.OUT Timing[4] 124 *.OUT Timing[3] 125 *.OUT Timing[2] 126 *.OUT Timing[1] 127 *.OUT Timing[0] 128 *.OUT Phi_to_Chans 129 *.IN PHI_in 130 *.OUT Phi_Delay 131 *.OUT Phase_A 132 *.IN RESET 133 *.OUT CAP 134 *.OUT Phase_B 135 *.VDD Delay_tile_S_i0.vdd0 136 *.GND Delay_tile_S_i0.gnd0 137 *.VDD Delay_tile_S_i0.vdd1 138 *.GND Delay_tile_S_i0.gnd2 139 *.VDD Delay_tile_S_i0.vdd2 140 *.VDD Delay_tile_S_i0.vdd3 141 *.GND Delay_tile_S_i0.gnd1 142 *.GND Delay_tile_S_i0.gnd3 143 *.VDD Delay_tile_S_i0.vdd4 144 *.GND Delay_tile_S_i0.gnd5 145 *.VDD Delay_tile_S_i0.vdd5 146 *.GND Delay_tile_S_i0.gnd6 147 *.IN Delay_tile_S_i0.input 131 *.INOUT Delay_tile_S_i0.inout4 134 *.OUT Delay_tile_S_i0.Out_to_Dff 64 *.OUT Delay_tile_S_i0.Timing 128 *.OUT Delay_tile_S_i0.output1 148 *.OUT Delay_tile_S_i0.output2 148 *.INOUT Delay_tile_S_i0.inout5 134 *.VDD Delay_tile_S_i1.vdd0 149 *.GND Delay_tile_S_i1.gnd0 150 *.VDD Delay_tile_S_i1.vdd1 151 *.GND Delay_tile_S_i1.gnd2 152 *.VDD Delay_tile_S_i1.vdd2 153 *.VDD Delay_tile_S_i1.vdd3 154 *.GND Delay_tile_S_i1.gnd1 155 *.GND Delay_tile_S_i1.gnd3 156 *.VDD Delay_tile_S_i1.vdd4 157 *.GND Delay_tile_S_i1.gnd5 158 *.VDD Delay_tile_S_i1.vdd5 159 *.GND Delay_tile_S_i1.gnd6 160 *.IN Delay_tile_S_i1.input 148 *.INOUT Delay_tile_S_i1.inout4 134 *.OUT Delay_tile_S_i1.Out_to_Dff 63 *.OUT Delay_tile_S_i1.Timing 127 *.OUT Delay_tile_S_i1.output1 161 *.OUT Delay_tile_S_i1.output2 161 *.INOUT Delay_tile_S_i1.inout5 134 *.VDD Delay_tile_S_i2.vdd0 162 *.GND Delay_tile_S_i2.gnd0 163 *.VDD Delay_tile_S_i2.vdd1 164 *.GND Delay_tile_S_i2.gnd2 165 *.VDD Delay_tile_S_i2.vdd2 166 *.VDD Delay_tile_S_i2.vdd3 167 *.GND Delay_tile_S_i2.gnd1 168 *.GND Delay_tile_S_i2.gnd3 169 *.VDD Delay_tile_S_i2.vdd4 170 *.GND Delay_tile_S_i2.gnd5 171 *.VDD Delay_tile_S_i2.vdd5 172 *.GND Delay_tile_S_i2.gnd6 173 *.IN Delay_tile_S_i2.input 161 *.INOUT Delay_tile_S_i2.inout4 134 *.OUT Delay_tile_S_i2.Out_to_Dff 62 *.OUT Delay_tile_S_i2.Timing 126 *.OUT Delay_tile_S_i2.output1 174 *.OUT Delay_tile_S_i2.output2 174 *.INOUT Delay_tile_S_i2.inout5 134 *.VDD Delay_tile_S_i3.vdd0 175 *.GND Delay_tile_S_i3.gnd0 176 *.VDD Delay_tile_S_i3.vdd1 177 *.GND Delay_tile_S_i3.gnd2 178 *.VDD Delay_tile_S_i3.vdd2 179 *.VDD Delay_tile_S_i3.vdd3 180 *.GND Delay_tile_S_i3.gnd1 181 *.GND Delay_tile_S_i3.gnd3 182 *.VDD Delay_tile_S_i3.vdd4 183 *.GND Delay_tile_S_i3.gnd5 184 *.VDD Delay_tile_S_i3.vdd5 185 *.GND Delay_tile_S_i3.gnd6 186 *.IN Delay_tile_S_i3.input 174 *.INOUT Delay_tile_S_i3.inout4 134 *.OUT Delay_tile_S_i3.Out_to_Dff 61 *.OUT Delay_tile_S_i3.Timing 125 *.OUT Delay_tile_S_i3.output1 187 *.OUT Delay_tile_S_i3.output2 187 *.INOUT Delay_tile_S_i3.inout5 134 *.VDD Delay_tile_S_i4.vdd0 188 *.GND Delay_tile_S_i4.gnd0 189 *.VDD Delay_tile_S_i4.vdd1 190 *.GND Delay_tile_S_i4.gnd2 191 *.VDD Delay_tile_S_i4.vdd2 192 *.VDD Delay_tile_S_i4.vdd3 193 *.GND Delay_tile_S_i4.gnd1 194 *.GND Delay_tile_S_i4.gnd3 195 *.VDD Delay_tile_S_i4.vdd4 196 *.GND Delay_tile_S_i4.gnd5 197 *.VDD Delay_tile_S_i4.vdd5 198 *.GND Delay_tile_S_i4.gnd6 199 *.IN Delay_tile_S_i4.input 187 *.INOUT Delay_tile_S_i4.inout4 134 *.OUT Delay_tile_S_i4.Out_to_Dff 60 *.OUT Delay_tile_S_i4.Timing 124 *.OUT Delay_tile_S_i4.output1 200 *.OUT Delay_tile_S_i4.output2 200 *.INOUT Delay_tile_S_i4.inout5 134 *.VDD Delay_tile_S_i5.vdd0 201 *.GND Delay_tile_S_i5.gnd0 202 *.VDD Delay_tile_S_i5.vdd1 203 *.GND Delay_tile_S_i5.gnd2 204 *.VDD Delay_tile_S_i5.vdd2 205 *.VDD Delay_tile_S_i5.vdd3 206 *.GND Delay_tile_S_i5.gnd1 207 *.GND Delay_tile_S_i5.gnd3 208 *.VDD Delay_tile_S_i5.vdd4 209 *.GND Delay_tile_S_i5.gnd5 210 *.VDD Delay_tile_S_i5.vdd5 211 *.GND Delay_tile_S_i5.gnd6 212 *.IN Delay_tile_S_i5.input 200 *.INOUT Delay_tile_S_i5.inout4 134 *.OUT Delay_tile_S_i5.Out_to_Dff 59 *.OUT Delay_tile_S_i5.Timing 123 *.OUT Delay_tile_S_i5.output1 213 *.OUT Delay_tile_S_i5.output2 213 *.INOUT Delay_tile_S_i5.inout5 134 *.VDD Delay_tile_S_i6.vdd0 214 *.GND Delay_tile_S_i6.gnd0 215 *.VDD Delay_tile_S_i6.vdd1 216 *.GND Delay_tile_S_i6.gnd2 217 *.VDD Delay_tile_S_i6.vdd2 218 *.VDD Delay_tile_S_i6.vdd3 219 *.GND Delay_tile_S_i6.gnd1 220 *.GND Delay_tile_S_i6.gnd3 221 *.VDD Delay_tile_S_i6.vdd4 222 *.GND Delay_tile_S_i6.gnd5 223 *.VDD Delay_tile_S_i6.vdd5 224 *.GND Delay_tile_S_i6.gnd6 225 *.IN Delay_tile_S_i6.input 213 *.INOUT Delay_tile_S_i6.inout4 134 *.OUT Delay_tile_S_i6.Out_to_Dff 58 *.OUT Delay_tile_S_i6.Timing 122 *.OUT Delay_tile_S_i6.output1 226 *.OUT Delay_tile_S_i6.output2 226 *.INOUT Delay_tile_S_i6.inout5 134 *.VDD Delay_tile_S_i7.vdd0 227 *.GND Delay_tile_S_i7.gnd0 228 *.VDD Delay_tile_S_i7.vdd1 229 *.GND Delay_tile_S_i7.gnd2 230 *.VDD Delay_tile_S_i7.vdd2 231 *.VDD Delay_tile_S_i7.vdd3 232 *.GND Delay_tile_S_i7.gnd1 233 *.GND Delay_tile_S_i7.gnd3 234 *.VDD Delay_tile_S_i7.vdd4 235 *.GND Delay_tile_S_i7.gnd5 236 *.VDD Delay_tile_S_i7.vdd5 237 *.GND Delay_tile_S_i7.gnd6 238 *.IN Delay_tile_S_i7.input 226 *.INOUT Delay_tile_S_i7.inout4 134 *.OUT Delay_tile_S_i7.Out_to_Dff 57 *.OUT Delay_tile_S_i7.Timing 121 *.OUT Delay_tile_S_i7.output1 239 *.OUT Delay_tile_S_i7.output2 239 *.INOUT Delay_tile_S_i7.inout5 134 *.VDD Delay_tile_S_i8.vdd0 240 *.GND Delay_tile_S_i8.gnd0 241 *.VDD Delay_tile_S_i8.vdd1 242 *.GND Delay_tile_S_i8.gnd2 243 *.VDD Delay_tile_S_i8.vdd2 244 *.VDD Delay_tile_S_i8.vdd3 245 *.GND Delay_tile_S_i8.gnd1 246 *.GND Delay_tile_S_i8.gnd3 247 *.VDD Delay_tile_S_i8.vdd4 248 *.GND Delay_tile_S_i8.gnd5 249 *.VDD Delay_tile_S_i8.vdd5 250 *.GND Delay_tile_S_i8.gnd6 251 *.IN Delay_tile_S_i8.input 239 *.INOUT Delay_tile_S_i8.inout4 134 *.OUT Delay_tile_S_i8.Out_to_Dff 56 *.OUT Delay_tile_S_i8.Timing 120 *.OUT Delay_tile_S_i8.output1 252 *.OUT Delay_tile_S_i8.output2 252 *.INOUT Delay_tile_S_i8.inout5 134 *.VDD Delay_tile_S_i9.vdd0 253 *.GND Delay_tile_S_i9.gnd0 254 *.VDD Delay_tile_S_i9.vdd1 255 *.GND Delay_tile_S_i9.gnd2 256 *.VDD Delay_tile_S_i9.vdd2 257 *.VDD Delay_tile_S_i9.vdd3 258 *.GND Delay_tile_S_i9.gnd1 259 *.GND Delay_tile_S_i9.gnd3 260 *.VDD Delay_tile_S_i9.vdd4 261 *.GND Delay_tile_S_i9.gnd5 262 *.VDD Delay_tile_S_i9.vdd5 263 *.GND Delay_tile_S_i9.gnd6 264 *.IN Delay_tile_S_i9.input 252 *.INOUT Delay_tile_S_i9.inout4 134 *.OUT Delay_tile_S_i9.Out_to_Dff 55 *.OUT Delay_tile_S_i9.Timing 119 *.OUT Delay_tile_S_i9.output1 265 *.OUT Delay_tile_S_i9.output2 265 *.INOUT Delay_tile_S_i9.inout5 134 *.VDD Delay_tile_S_i10.vdd0 266 *.GND Delay_tile_S_i10.gnd0 267 *.VDD Delay_tile_S_i10.vdd1 268 *.GND Delay_tile_S_i10.gnd2 269 *.VDD Delay_tile_S_i10.vdd2 270 *.VDD Delay_tile_S_i10.vdd3 271 *.GND Delay_tile_S_i10.gnd1 272 *.GND Delay_tile_S_i10.gnd3 273 *.VDD Delay_tile_S_i10.vdd4 274 *.GND Delay_tile_S_i10.gnd5 275 *.VDD Delay_tile_S_i10.vdd5 276 *.GND Delay_tile_S_i10.gnd6 277 *.IN Delay_tile_S_i10.input 265 *.INOUT Delay_tile_S_i10.inout4 134 *.OUT Delay_tile_S_i10.Out_to_Dff 54 *.OUT Delay_tile_S_i10.Timing 118 *.OUT Delay_tile_S_i10.output1 278 *.OUT Delay_tile_S_i10.output2 278 *.INOUT Delay_tile_S_i10.inout5 134 *.VDD Delay_tile_S_i11.vdd0 279 *.GND Delay_tile_S_i11.gnd0 280 *.VDD Delay_tile_S_i11.vdd1 281 *.GND Delay_tile_S_i11.gnd2 282 *.VDD Delay_tile_S_i11.vdd2 283 *.VDD Delay_tile_S_i11.vdd3 284 *.GND Delay_tile_S_i11.gnd1 285 *.GND Delay_tile_S_i11.gnd3 286 *.VDD Delay_tile_S_i11.vdd4 287 *.GND Delay_tile_S_i11.gnd5 288 *.VDD Delay_tile_S_i11.vdd5 289 *.GND Delay_tile_S_i11.gnd6 290 *.IN Delay_tile_S_i11.input 278 *.INOUT Delay_tile_S_i11.inout4 134 *.OUT Delay_tile_S_i11.Out_to_Dff 53 *.OUT Delay_tile_S_i11.Timing 117 *.OUT Delay_tile_S_i11.output1 291 *.OUT Delay_tile_S_i11.output2 291 *.INOUT Delay_tile_S_i11.inout5 134 *.VDD Delay_tile_S_i12.vdd0 292 *.GND Delay_tile_S_i12.gnd0 293 *.VDD Delay_tile_S_i12.vdd1 294 *.GND Delay_tile_S_i12.gnd2 295 *.VDD Delay_tile_S_i12.vdd2 296 *.VDD Delay_tile_S_i12.vdd3 297 *.GND Delay_tile_S_i12.gnd1 298 *.GND Delay_tile_S_i12.gnd3 299 *.VDD Delay_tile_S_i12.vdd4 300 *.GND Delay_tile_S_i12.gnd5 301 *.VDD Delay_tile_S_i12.vdd5 302 *.GND Delay_tile_S_i12.gnd6 303 *.IN Delay_tile_S_i12.input 291 *.INOUT Delay_tile_S_i12.inout4 134 *.OUT Delay_tile_S_i12.Out_to_Dff 52 *.OUT Delay_tile_S_i12.Timing 116 *.OUT Delay_tile_S_i12.output1 304 *.OUT Delay_tile_S_i12.output2 304 *.INOUT Delay_tile_S_i12.inout5 134 *.VDD Delay_tile_S_i13.vdd0 305 *.GND Delay_tile_S_i13.gnd0 306 *.VDD Delay_tile_S_i13.vdd1 307 *.GND Delay_tile_S_i13.gnd2 308 *.VDD Delay_tile_S_i13.vdd2 309 *.VDD Delay_tile_S_i13.vdd3 310 *.GND Delay_tile_S_i13.gnd1 311 *.GND Delay_tile_S_i13.gnd3 312 *.VDD Delay_tile_S_i13.vdd4 313 *.GND Delay_tile_S_i13.gnd5 314 *.VDD Delay_tile_S_i13.vdd5 315 *.GND Delay_tile_S_i13.gnd6 316 *.IN Delay_tile_S_i13.input 304 *.INOUT Delay_tile_S_i13.inout4 134 *.OUT Delay_tile_S_i13.Out_to_Dff 51 *.OUT Delay_tile_S_i13.Timing 115 *.OUT Delay_tile_S_i13.output1 317 *.OUT Delay_tile_S_i13.output2 317 *.INOUT Delay_tile_S_i13.inout5 134 *.VDD Delay_tile_S_i14.vdd0 318 *.GND Delay_tile_S_i14.gnd0 319 *.VDD Delay_tile_S_i14.vdd1 320 *.GND Delay_tile_S_i14.gnd2 321 *.VDD Delay_tile_S_i14.vdd2 322 *.VDD Delay_tile_S_i14.vdd3 323 *.GND Delay_tile_S_i14.gnd1 324 *.GND Delay_tile_S_i14.gnd3 325 *.VDD Delay_tile_S_i14.vdd4 326 *.GND Delay_tile_S_i14.gnd5 327 *.VDD Delay_tile_S_i14.vdd5 328 *.GND Delay_tile_S_i14.gnd6 329 *.IN Delay_tile_S_i14.input 317 *.INOUT Delay_tile_S_i14.inout4 134 *.OUT Delay_tile_S_i14.Out_to_Dff 50 *.OUT Delay_tile_S_i14.Timing 114 *.OUT Delay_tile_S_i14.output1 330 *.OUT Delay_tile_S_i14.output2 330 *.INOUT Delay_tile_S_i14.inout5 134 *.VDD Delay_tile_S_i15.vdd0 331 *.GND Delay_tile_S_i15.gnd0 332 *.VDD Delay_tile_S_i15.vdd1 333 *.GND Delay_tile_S_i15.gnd2 334 *.VDD Delay_tile_S_i15.vdd2 335 *.VDD Delay_tile_S_i15.vdd3 336 *.GND Delay_tile_S_i15.gnd1 337 *.GND Delay_tile_S_i15.gnd3 338 *.VDD Delay_tile_S_i15.vdd4 339 *.GND Delay_tile_S_i15.gnd5 340 *.VDD Delay_tile_S_i15.vdd5 341 *.GND Delay_tile_S_i15.gnd6 342 *.IN Delay_tile_S_i15.input 330 *.INOUT Delay_tile_S_i15.inout4 134 *.OUT Delay_tile_S_i15.Out_to_Dff 49 *.OUT Delay_tile_S_i15.Timing 113 *.OUT Delay_tile_S_i15.output1 343 *.OUT Delay_tile_S_i15.output2 343 *.INOUT Delay_tile_S_i15.inout5 134 *.VDD Delay_tile_S_i16.vdd0 344 *.GND Delay_tile_S_i16.gnd0 345 *.VDD Delay_tile_S_i16.vdd1 346 *.GND Delay_tile_S_i16.gnd2 347 *.VDD Delay_tile_S_i16.vdd2 348 *.VDD Delay_tile_S_i16.vdd3 349 *.GND Delay_tile_S_i16.gnd1 350 *.GND Delay_tile_S_i16.gnd3 351 *.VDD Delay_tile_S_i16.vdd4 352 *.GND Delay_tile_S_i16.gnd5 353 *.VDD Delay_tile_S_i16.vdd5 354 *.GND Delay_tile_S_i16.gnd6 355 *.IN Delay_tile_S_i16.input 343 *.INOUT Delay_tile_S_i16.inout4 134 *.OUT Delay_tile_S_i16.Out_to_Dff 48 *.OUT Delay_tile_S_i16.Timing 112 *.OUT Delay_tile_S_i16.output1 356 *.OUT Delay_tile_S_i16.output2 356 *.INOUT Delay_tile_S_i16.inout5 134 *.VDD Delay_tile_S_i17.vdd0 357 *.GND Delay_tile_S_i17.gnd0 358 *.VDD Delay_tile_S_i17.vdd1 359 *.GND Delay_tile_S_i17.gnd2 360 *.VDD Delay_tile_S_i17.vdd2 361 *.VDD Delay_tile_S_i17.vdd3 362 *.GND Delay_tile_S_i17.gnd1 363 *.GND Delay_tile_S_i17.gnd3 364 *.VDD Delay_tile_S_i17.vdd4 365 *.GND Delay_tile_S_i17.gnd5 366 *.VDD Delay_tile_S_i17.vdd5 367 *.GND Delay_tile_S_i17.gnd6 368 *.IN Delay_tile_S_i17.input 356 *.INOUT Delay_tile_S_i17.inout4 134 *.OUT Delay_tile_S_i17.Out_to_Dff 47 *.OUT Delay_tile_S_i17.Timing 111 *.OUT Delay_tile_S_i17.output1 369 *.OUT Delay_tile_S_i17.output2 369 *.INOUT Delay_tile_S_i17.inout5 134 *.VDD Delay_tile_S_i18.vdd0 370 *.GND Delay_tile_S_i18.gnd0 371 *.VDD Delay_tile_S_i18.vdd1 372 *.GND Delay_tile_S_i18.gnd2 373 *.VDD Delay_tile_S_i18.vdd2 374 *.VDD Delay_tile_S_i18.vdd3 375 *.GND Delay_tile_S_i18.gnd1 376 *.GND Delay_tile_S_i18.gnd3 377 *.VDD Delay_tile_S_i18.vdd4 378 *.GND Delay_tile_S_i18.gnd5 379 *.VDD Delay_tile_S_i18.vdd5 380 *.GND Delay_tile_S_i18.gnd6 381 *.IN Delay_tile_S_i18.input 369 *.INOUT Delay_tile_S_i18.inout4 134 *.OUT Delay_tile_S_i18.Out_to_Dff 46 *.OUT Delay_tile_S_i18.Timing 110 *.OUT Delay_tile_S_i18.output1 382 *.OUT Delay_tile_S_i18.output2 382 *.INOUT Delay_tile_S_i18.inout5 134 *.VDD Delay_tile_S_i19.vdd0 383 *.GND Delay_tile_S_i19.gnd0 384 *.VDD Delay_tile_S_i19.vdd1 385 *.GND Delay_tile_S_i19.gnd2 386 *.VDD Delay_tile_S_i19.vdd2 387 *.VDD Delay_tile_S_i19.vdd3 388 *.GND Delay_tile_S_i19.gnd1 389 *.GND Delay_tile_S_i19.gnd3 390 *.VDD Delay_tile_S_i19.vdd4 391 *.GND Delay_tile_S_i19.gnd5 392 *.VDD Delay_tile_S_i19.vdd5 393 *.GND Delay_tile_S_i19.gnd6 394 *.IN Delay_tile_S_i19.input 382 *.INOUT Delay_tile_S_i19.inout4 134 *.OUT Delay_tile_S_i19.Out_to_Dff 45 *.OUT Delay_tile_S_i19.Timing 109 *.OUT Delay_tile_S_i19.output1 395 *.OUT Delay_tile_S_i19.output2 395 *.INOUT Delay_tile_S_i19.inout5 134 *.VDD Delay_tile_S_i20.vdd0 396 *.GND Delay_tile_S_i20.gnd0 397 *.VDD Delay_tile_S_i20.vdd1 398 *.GND Delay_tile_S_i20.gnd2 399 *.VDD Delay_tile_S_i20.vdd2 400 *.VDD Delay_tile_S_i20.vdd3 401 *.GND Delay_tile_S_i20.gnd1 402 *.GND Delay_tile_S_i20.gnd3 403 *.VDD Delay_tile_S_i20.vdd4 404 *.GND Delay_tile_S_i20.gnd5 405 *.VDD Delay_tile_S_i20.vdd5 406 *.GND Delay_tile_S_i20.gnd6 407 *.IN Delay_tile_S_i20.input 395 *.INOUT Delay_tile_S_i20.inout4 134 *.OUT Delay_tile_S_i20.Out_to_Dff 44 *.OUT Delay_tile_S_i20.Timing 108 *.OUT Delay_tile_S_i20.output1 408 *.OUT Delay_tile_S_i20.output2 408 *.INOUT Delay_tile_S_i20.inout5 134 *.VDD Delay_tile_S_i21.vdd0 409 *.GND Delay_tile_S_i21.gnd0 410 *.VDD Delay_tile_S_i21.vdd1 411 *.GND Delay_tile_S_i21.gnd2 412 *.VDD Delay_tile_S_i21.vdd2 413 *.VDD Delay_tile_S_i21.vdd3 414 *.GND Delay_tile_S_i21.gnd1 415 *.GND Delay_tile_S_i21.gnd3 416 *.VDD Delay_tile_S_i21.vdd4 417 *.GND Delay_tile_S_i21.gnd5 418 *.VDD Delay_tile_S_i21.vdd5 419 *.GND Delay_tile_S_i21.gnd6 420 *.IN Delay_tile_S_i21.input 408 *.INOUT Delay_tile_S_i21.inout4 134 *.OUT Delay_tile_S_i21.Out_to_Dff 43 *.OUT Delay_tile_S_i21.Timing 107 *.OUT Delay_tile_S_i21.output1 421 *.OUT Delay_tile_S_i21.output2 421 *.INOUT Delay_tile_S_i21.inout5 134 *.VDD Delay_tile_S_i22.vdd0 422 *.GND Delay_tile_S_i22.gnd0 423 *.VDD Delay_tile_S_i22.vdd1 424 *.GND Delay_tile_S_i22.gnd2 425 *.VDD Delay_tile_S_i22.vdd2 426 *.VDD Delay_tile_S_i22.vdd3 427 *.GND Delay_tile_S_i22.gnd1 428 *.GND Delay_tile_S_i22.gnd3 429 *.VDD Delay_tile_S_i22.vdd4 430 *.GND Delay_tile_S_i22.gnd5 431 *.VDD Delay_tile_S_i22.vdd5 432 *.GND Delay_tile_S_i22.gnd6 433 *.IN Delay_tile_S_i22.input 421 *.INOUT Delay_tile_S_i22.inout4 134 *.OUT Delay_tile_S_i22.Out_to_Dff 42 *.OUT Delay_tile_S_i22.Timing 106 *.OUT Delay_tile_S_i22.output1 434 *.OUT Delay_tile_S_i22.output2 434 *.INOUT Delay_tile_S_i22.inout5 134 *.VDD Delay_tile_S_i23.vdd0 435 *.GND Delay_tile_S_i23.gnd0 436 *.VDD Delay_tile_S_i23.vdd1 437 *.GND Delay_tile_S_i23.gnd2 438 *.VDD Delay_tile_S_i23.vdd2 439 *.VDD Delay_tile_S_i23.vdd3 440 *.GND Delay_tile_S_i23.gnd1 441 *.GND Delay_tile_S_i23.gnd3 442 *.VDD Delay_tile_S_i23.vdd4 443 *.GND Delay_tile_S_i23.gnd5 444 *.VDD Delay_tile_S_i23.vdd5 445 *.GND Delay_tile_S_i23.gnd6 446 *.IN Delay_tile_S_i23.input 434 *.INOUT Delay_tile_S_i23.inout4 134 *.OUT Delay_tile_S_i23.Out_to_Dff 41 *.OUT Delay_tile_S_i23.Timing 105 *.OUT Delay_tile_S_i23.output1 447 *.OUT Delay_tile_S_i23.output2 447 *.INOUT Delay_tile_S_i23.inout5 134 *.VDD Delay_tile_S_i24.vdd0 448 *.GND Delay_tile_S_i24.gnd0 449 *.VDD Delay_tile_S_i24.vdd1 450 *.GND Delay_tile_S_i24.gnd2 451 *.VDD Delay_tile_S_i24.vdd2 452 *.VDD Delay_tile_S_i24.vdd3 453 *.GND Delay_tile_S_i24.gnd1 454 *.GND Delay_tile_S_i24.gnd3 455 *.VDD Delay_tile_S_i24.vdd4 456 *.GND Delay_tile_S_i24.gnd5 457 *.VDD Delay_tile_S_i24.vdd5 458 *.GND Delay_tile_S_i24.gnd6 459 *.IN Delay_tile_S_i24.input 447 *.INOUT Delay_tile_S_i24.inout4 134 *.OUT Delay_tile_S_i24.Out_to_Dff 40 *.OUT Delay_tile_S_i24.Timing 104 *.OUT Delay_tile_S_i24.output1 460 *.OUT Delay_tile_S_i24.output2 460 *.INOUT Delay_tile_S_i24.inout5 134 *.VDD Delay_tile_S_i25.vdd0 461 *.GND Delay_tile_S_i25.gnd0 462 *.VDD Delay_tile_S_i25.vdd1 463 *.GND Delay_tile_S_i25.gnd2 464 *.VDD Delay_tile_S_i25.vdd2 465 *.VDD Delay_tile_S_i25.vdd3 466 *.GND Delay_tile_S_i25.gnd1 467 *.GND Delay_tile_S_i25.gnd3 468 *.VDD Delay_tile_S_i25.vdd4 469 *.GND Delay_tile_S_i25.gnd5 470 *.VDD Delay_tile_S_i25.vdd5 471 *.GND Delay_tile_S_i25.gnd6 472 *.IN Delay_tile_S_i25.input 460 *.INOUT Delay_tile_S_i25.inout4 134 *.OUT Delay_tile_S_i25.Out_to_Dff 39 *.OUT Delay_tile_S_i25.Timing 103 *.OUT Delay_tile_S_i25.output1 473 *.OUT Delay_tile_S_i25.output2 473 *.INOUT Delay_tile_S_i25.inout5 134 *.VDD Delay_tile_S_i26.vdd0 474 *.GND Delay_tile_S_i26.gnd0 475 *.VDD Delay_tile_S_i26.vdd1 476 *.GND Delay_tile_S_i26.gnd2 477 *.VDD Delay_tile_S_i26.vdd2 478 *.VDD Delay_tile_S_i26.vdd3 479 *.GND Delay_tile_S_i26.gnd1 480 *.GND Delay_tile_S_i26.gnd3 481 *.VDD Delay_tile_S_i26.vdd4 482 *.GND Delay_tile_S_i26.gnd5 483 *.VDD Delay_tile_S_i26.vdd5 484 *.GND Delay_tile_S_i26.gnd6 485 *.IN Delay_tile_S_i26.input 473 *.INOUT Delay_tile_S_i26.inout4 134 *.OUT Delay_tile_S_i26.Out_to_Dff 38 *.OUT Delay_tile_S_i26.Timing 102 *.OUT Delay_tile_S_i26.output1 486 *.OUT Delay_tile_S_i26.output2 486 *.INOUT Delay_tile_S_i26.inout5 134 *.VDD Delay_tile_S_i27.vdd0 487 *.GND Delay_tile_S_i27.gnd0 488 *.VDD Delay_tile_S_i27.vdd1 489 *.GND Delay_tile_S_i27.gnd2 490 *.VDD Delay_tile_S_i27.vdd2 491 *.VDD Delay_tile_S_i27.vdd3 492 *.GND Delay_tile_S_i27.gnd1 493 *.GND Delay_tile_S_i27.gnd3 494 *.VDD Delay_tile_S_i27.vdd4 495 *.GND Delay_tile_S_i27.gnd5 496 *.VDD Delay_tile_S_i27.vdd5 497 *.GND Delay_tile_S_i27.gnd6 498 *.IN Delay_tile_S_i27.input 486 *.INOUT Delay_tile_S_i27.inout4 134 *.OUT Delay_tile_S_i27.Out_to_Dff 37 *.OUT Delay_tile_S_i27.Timing 101 *.OUT Delay_tile_S_i27.output1 499 *.OUT Delay_tile_S_i27.output2 499 *.INOUT Delay_tile_S_i27.inout5 134 *.VDD Delay_tile_S_i28.vdd0 500 *.GND Delay_tile_S_i28.gnd0 501 *.VDD Delay_tile_S_i28.vdd1 502 *.GND Delay_tile_S_i28.gnd2 503 *.VDD Delay_tile_S_i28.vdd2 504 *.VDD Delay_tile_S_i28.vdd3 505 *.GND Delay_tile_S_i28.gnd1 506 *.GND Delay_tile_S_i28.gnd3 507 *.VDD Delay_tile_S_i28.vdd4 508 *.GND Delay_tile_S_i28.gnd5 509 *.VDD Delay_tile_S_i28.vdd5 510 *.GND Delay_tile_S_i28.gnd6 511 *.IN Delay_tile_S_i28.input 499 *.INOUT Delay_tile_S_i28.inout4 134 *.OUT Delay_tile_S_i28.Out_to_Dff 36 *.OUT Delay_tile_S_i28.Timing 100 *.OUT Delay_tile_S_i28.output1 512 *.OUT Delay_tile_S_i28.output2 512 *.INOUT Delay_tile_S_i28.inout5 134 *.VDD Delay_tile_S_i29.vdd0 513 *.GND Delay_tile_S_i29.gnd0 514 *.VDD Delay_tile_S_i29.vdd1 515 *.GND Delay_tile_S_i29.gnd2 516 *.VDD Delay_tile_S_i29.vdd2 517 *.VDD Delay_tile_S_i29.vdd3 518 *.GND Delay_tile_S_i29.gnd1 519 *.GND Delay_tile_S_i29.gnd3 520 *.VDD Delay_tile_S_i29.vdd4 521 *.GND Delay_tile_S_i29.gnd5 522 *.VDD Delay_tile_S_i29.vdd5 523 *.GND Delay_tile_S_i29.gnd6 524 *.IN Delay_tile_S_i29.input 512 *.INOUT Delay_tile_S_i29.inout4 134 *.OUT Delay_tile_S_i29.Out_to_Dff 35 *.OUT Delay_tile_S_i29.Timing 99 *.OUT Delay_tile_S_i29.output1 525 *.OUT Delay_tile_S_i29.output2 525 *.INOUT Delay_tile_S_i29.inout5 134 *.VDD Delay_tile_S_i30.vdd0 526 *.GND Delay_tile_S_i30.gnd0 527 *.VDD Delay_tile_S_i30.vdd1 528 *.GND Delay_tile_S_i30.gnd2 529 *.VDD Delay_tile_S_i30.vdd2 530 *.VDD Delay_tile_S_i30.vdd3 531 *.GND Delay_tile_S_i30.gnd1 532 *.GND Delay_tile_S_i30.gnd3 533 *.VDD Delay_tile_S_i30.vdd4 534 *.GND Delay_tile_S_i30.gnd5 535 *.VDD Delay_tile_S_i30.vdd5 536 *.GND Delay_tile_S_i30.gnd6 537 *.IN Delay_tile_S_i30.input 525 *.INOUT Delay_tile_S_i30.inout4 134 *.OUT Delay_tile_S_i30.Out_to_Dff 34 *.OUT Delay_tile_S_i30.Timing 98 *.OUT Delay_tile_S_i30.output1 538 *.OUT Delay_tile_S_i30.output2 538 *.INOUT Delay_tile_S_i30.inout5 134 *.VDD Delay_tile_S_i31.vdd0 539 *.GND Delay_tile_S_i31.gnd0 540 *.VDD Delay_tile_S_i31.vdd1 541 *.GND Delay_tile_S_i31.gnd2 542 *.VDD Delay_tile_S_i31.vdd2 543 *.VDD Delay_tile_S_i31.vdd3 544 *.GND Delay_tile_S_i31.gnd1 545 *.GND Delay_tile_S_i31.gnd3 546 *.VDD Delay_tile_S_i31.vdd4 547 *.GND Delay_tile_S_i31.gnd5 548 *.VDD Delay_tile_S_i31.vdd5 549 *.GND Delay_tile_S_i31.gnd6 550 *.IN Delay_tile_S_i31.input 538 *.INOUT Delay_tile_S_i31.inout4 134 *.OUT Delay_tile_S_i31.Out_to_Dff 33 *.OUT Delay_tile_S_i31.Timing 97 *.OUT Delay_tile_S_i31.output1 551 *.OUT Delay_tile_S_i31.output2 551 *.INOUT Delay_tile_S_i31.inout5 134 *.VDD Delay_tile_S_i32.vdd0 552 *.GND Delay_tile_S_i32.gnd0 553 *.VDD Delay_tile_S_i32.vdd1 554 *.GND Delay_tile_S_i32.gnd2 555 *.VDD Delay_tile_S_i32.vdd2 556 *.VDD Delay_tile_S_i32.vdd3 557 *.GND Delay_tile_S_i32.gnd1 558 *.GND Delay_tile_S_i32.gnd3 559 *.VDD Delay_tile_S_i32.vdd4 560 *.GND Delay_tile_S_i32.gnd5 561 *.VDD Delay_tile_S_i32.vdd5 562 *.GND Delay_tile_S_i32.gnd6 563 *.IN Delay_tile_S_i32.input 551 *.INOUT Delay_tile_S_i32.inout4 134 *.OUT Delay_tile_S_i32.Out_to_Dff 32 *.OUT Delay_tile_S_i32.Timing 96 *.OUT Delay_tile_S_i32.output1 564 *.OUT Delay_tile_S_i32.output2 564 *.INOUT Delay_tile_S_i32.inout5 134 *.VDD Delay_tile_S_i33.vdd0 565 *.GND Delay_tile_S_i33.gnd0 566 *.VDD Delay_tile_S_i33.vdd1 567 *.GND Delay_tile_S_i33.gnd2 568 *.VDD Delay_tile_S_i33.vdd2 569 *.VDD Delay_tile_S_i33.vdd3 570 *.GND Delay_tile_S_i33.gnd1 571 *.GND Delay_tile_S_i33.gnd3 572 *.VDD Delay_tile_S_i33.vdd4 573 *.GND Delay_tile_S_i33.gnd5 574 *.VDD Delay_tile_S_i33.vdd5 575 *.GND Delay_tile_S_i33.gnd6 576 *.IN Delay_tile_S_i33.input 564 *.INOUT Delay_tile_S_i33.inout4 134 *.OUT Delay_tile_S_i33.Out_to_Dff 31 *.OUT Delay_tile_S_i33.Timing 95 *.OUT Delay_tile_S_i33.output1 577 *.OUT Delay_tile_S_i33.output2 577 *.INOUT Delay_tile_S_i33.inout5 134 *.VDD Delay_tile_S_i34.vdd0 578 *.GND Delay_tile_S_i34.gnd0 579 *.VDD Delay_tile_S_i34.vdd1 580 *.GND Delay_tile_S_i34.gnd2 581 *.VDD Delay_tile_S_i34.vdd2 582 *.VDD Delay_tile_S_i34.vdd3 583 *.GND Delay_tile_S_i34.gnd1 584 *.GND Delay_tile_S_i34.gnd3 585 *.VDD Delay_tile_S_i34.vdd4 586 *.GND Delay_tile_S_i34.gnd5 587 *.VDD Delay_tile_S_i34.vdd5 588 *.GND Delay_tile_S_i34.gnd6 589 *.IN Delay_tile_S_i34.input 577 *.INOUT Delay_tile_S_i34.inout4 134 *.OUT Delay_tile_S_i34.Out_to_Dff 30 *.OUT Delay_tile_S_i34.Timing 94 *.OUT Delay_tile_S_i34.output1 590 *.OUT Delay_tile_S_i34.output2 590 *.INOUT Delay_tile_S_i34.inout5 134 *.VDD Delay_tile_S_i35.vdd0 591 *.GND Delay_tile_S_i35.gnd0 592 *.VDD Delay_tile_S_i35.vdd1 593 *.GND Delay_tile_S_i35.gnd2 594 *.VDD Delay_tile_S_i35.vdd2 595 *.VDD Delay_tile_S_i35.vdd3 596 *.GND Delay_tile_S_i35.gnd1 597 *.GND Delay_tile_S_i35.gnd3 598 *.VDD Delay_tile_S_i35.vdd4 599 *.GND Delay_tile_S_i35.gnd5 600 *.VDD Delay_tile_S_i35.vdd5 601 *.GND Delay_tile_S_i35.gnd6 602 *.IN Delay_tile_S_i35.input 590 *.INOUT Delay_tile_S_i35.inout4 134 *.OUT Delay_tile_S_i35.Out_to_Dff 29 *.OUT Delay_tile_S_i35.Timing 93 *.OUT Delay_tile_S_i35.output1 603 *.OUT Delay_tile_S_i35.output2 603 *.INOUT Delay_tile_S_i35.inout5 134 *.VDD Delay_tile_S_i36.vdd0 604 *.GND Delay_tile_S_i36.gnd0 605 *.VDD Delay_tile_S_i36.vdd1 606 *.GND Delay_tile_S_i36.gnd2 607 *.VDD Delay_tile_S_i36.vdd2 608 *.VDD Delay_tile_S_i36.vdd3 609 *.GND Delay_tile_S_i36.gnd1 610 *.GND Delay_tile_S_i36.gnd3 611 *.VDD Delay_tile_S_i36.vdd4 612 *.GND Delay_tile_S_i36.gnd5 613 *.VDD Delay_tile_S_i36.vdd5 614 *.GND Delay_tile_S_i36.gnd6 615 *.IN Delay_tile_S_i36.input 603 *.INOUT Delay_tile_S_i36.inout4 134 *.OUT Delay_tile_S_i36.Out_to_Dff 28 *.OUT Delay_tile_S_i36.Timing 92 *.OUT Delay_tile_S_i36.output1 616 *.OUT Delay_tile_S_i36.output2 616 *.INOUT Delay_tile_S_i36.inout5 134 *.VDD Delay_tile_S_i37.vdd0 617 *.GND Delay_tile_S_i37.gnd0 618 *.VDD Delay_tile_S_i37.vdd1 619 *.GND Delay_tile_S_i37.gnd2 620 *.VDD Delay_tile_S_i37.vdd2 621 *.VDD Delay_tile_S_i37.vdd3 622 *.GND Delay_tile_S_i37.gnd1 623 *.GND Delay_tile_S_i37.gnd3 624 *.VDD Delay_tile_S_i37.vdd4 625 *.GND Delay_tile_S_i37.gnd5 626 *.VDD Delay_tile_S_i37.vdd5 627 *.GND Delay_tile_S_i37.gnd6 628 *.IN Delay_tile_S_i37.input 616 *.INOUT Delay_tile_S_i37.inout4 134 *.OUT Delay_tile_S_i37.Out_to_Dff 27 *.OUT Delay_tile_S_i37.Timing 91 *.OUT Delay_tile_S_i37.output1 629 *.OUT Delay_tile_S_i37.output2 629 *.INOUT Delay_tile_S_i37.inout5 134 *.VDD Delay_tile_S_i38.vdd0 630 *.GND Delay_tile_S_i38.gnd0 631 *.VDD Delay_tile_S_i38.vdd1 632 *.GND Delay_tile_S_i38.gnd2 633 *.VDD Delay_tile_S_i38.vdd2 634 *.VDD Delay_tile_S_i38.vdd3 635 *.GND Delay_tile_S_i38.gnd1 636 *.GND Delay_tile_S_i38.gnd3 637 *.VDD Delay_tile_S_i38.vdd4 638 *.GND Delay_tile_S_i38.gnd5 639 *.VDD Delay_tile_S_i38.vdd5 640 *.GND Delay_tile_S_i38.gnd6 641 *.IN Delay_tile_S_i38.input 629 *.INOUT Delay_tile_S_i38.inout4 134 *.OUT Delay_tile_S_i38.Out_to_Dff 26 *.OUT Delay_tile_S_i38.Timing 90 *.OUT Delay_tile_S_i38.output1 642 *.OUT Delay_tile_S_i38.output2 642 *.INOUT Delay_tile_S_i38.inout5 134 *.VDD Delay_tile_S_i39.vdd0 643 *.GND Delay_tile_S_i39.gnd0 644 *.VDD Delay_tile_S_i39.vdd1 645 *.GND Delay_tile_S_i39.gnd2 646 *.VDD Delay_tile_S_i39.vdd2 647 *.VDD Delay_tile_S_i39.vdd3 648 *.GND Delay_tile_S_i39.gnd1 649 *.GND Delay_tile_S_i39.gnd3 650 *.VDD Delay_tile_S_i39.vdd4 651 *.GND Delay_tile_S_i39.gnd5 652 *.VDD Delay_tile_S_i39.vdd5 653 *.GND Delay_tile_S_i39.gnd6 654 *.IN Delay_tile_S_i39.input 642 *.INOUT Delay_tile_S_i39.inout4 134 *.OUT Delay_tile_S_i39.Out_to_Dff 25 *.OUT Delay_tile_S_i39.Timing 89 *.OUT Delay_tile_S_i39.output1 655 *.OUT Delay_tile_S_i39.output2 655 *.INOUT Delay_tile_S_i39.inout5 134 *.VDD Delay_tile_S_i40.vdd0 656 *.GND Delay_tile_S_i40.gnd0 657 *.VDD Delay_tile_S_i40.vdd1 658 *.GND Delay_tile_S_i40.gnd2 659 *.VDD Delay_tile_S_i40.vdd2 660 *.VDD Delay_tile_S_i40.vdd3 661 *.GND Delay_tile_S_i40.gnd1 662 *.GND Delay_tile_S_i40.gnd3 663 *.VDD Delay_tile_S_i40.vdd4 664 *.GND Delay_tile_S_i40.gnd5 665 *.VDD Delay_tile_S_i40.vdd5 666 *.GND Delay_tile_S_i40.gnd6 667 *.IN Delay_tile_S_i40.input 655 *.INOUT Delay_tile_S_i40.inout4 134 *.OUT Delay_tile_S_i40.Out_to_Dff 24 *.OUT Delay_tile_S_i40.Timing 88 *.OUT Delay_tile_S_i40.output1 668 *.OUT Delay_tile_S_i40.output2 668 *.INOUT Delay_tile_S_i40.inout5 134 *.VDD Delay_tile_S_i41.vdd0 669 *.GND Delay_tile_S_i41.gnd0 670 *.VDD Delay_tile_S_i41.vdd1 671 *.GND Delay_tile_S_i41.gnd2 672 *.VDD Delay_tile_S_i41.vdd2 673 *.VDD Delay_tile_S_i41.vdd3 674 *.GND Delay_tile_S_i41.gnd1 675 *.GND Delay_tile_S_i41.gnd3 676 *.VDD Delay_tile_S_i41.vdd4 677 *.GND Delay_tile_S_i41.gnd5 678 *.VDD Delay_tile_S_i41.vdd5 679 *.GND Delay_tile_S_i41.gnd6 680 *.IN Delay_tile_S_i41.input 668 *.INOUT Delay_tile_S_i41.inout4 134 *.OUT Delay_tile_S_i41.Out_to_Dff 23 *.OUT Delay_tile_S_i41.Timing 87 *.OUT Delay_tile_S_i41.output1 681 *.OUT Delay_tile_S_i41.output2 681 *.INOUT Delay_tile_S_i41.inout5 134 *.VDD Delay_tile_S_i42.vdd0 682 *.GND Delay_tile_S_i42.gnd0 683 *.VDD Delay_tile_S_i42.vdd1 684 *.GND Delay_tile_S_i42.gnd2 685 *.VDD Delay_tile_S_i42.vdd2 686 *.VDD Delay_tile_S_i42.vdd3 687 *.GND Delay_tile_S_i42.gnd1 688 *.GND Delay_tile_S_i42.gnd3 689 *.VDD Delay_tile_S_i42.vdd4 690 *.GND Delay_tile_S_i42.gnd5 691 *.VDD Delay_tile_S_i42.vdd5 692 *.GND Delay_tile_S_i42.gnd6 693 *.IN Delay_tile_S_i42.input 681 *.INOUT Delay_tile_S_i42.inout4 134 *.OUT Delay_tile_S_i42.Out_to_Dff 22 *.OUT Delay_tile_S_i42.Timing 86 *.OUT Delay_tile_S_i42.output1 694 *.OUT Delay_tile_S_i42.output2 694 *.INOUT Delay_tile_S_i42.inout5 134 *.VDD Delay_tile_S_i43.vdd0 695 *.GND Delay_tile_S_i43.gnd0 696 *.VDD Delay_tile_S_i43.vdd1 697 *.GND Delay_tile_S_i43.gnd2 698 *.VDD Delay_tile_S_i43.vdd2 699 *.VDD Delay_tile_S_i43.vdd3 700 *.GND Delay_tile_S_i43.gnd1 701 *.GND Delay_tile_S_i43.gnd3 702 *.VDD Delay_tile_S_i43.vdd4 703 *.GND Delay_tile_S_i43.gnd5 704 *.VDD Delay_tile_S_i43.vdd5 705 *.GND Delay_tile_S_i43.gnd6 706 *.IN Delay_tile_S_i43.input 694 *.INOUT Delay_tile_S_i43.inout4 134 *.OUT Delay_tile_S_i43.Out_to_Dff 21 *.OUT Delay_tile_S_i43.Timing 85 *.OUT Delay_tile_S_i43.output1 707 *.OUT Delay_tile_S_i43.output2 707 *.INOUT Delay_tile_S_i43.inout5 134 *.VDD Delay_tile_S_i44.vdd0 708 *.GND Delay_tile_S_i44.gnd0 709 *.VDD Delay_tile_S_i44.vdd1 710 *.GND Delay_tile_S_i44.gnd2 711 *.VDD Delay_tile_S_i44.vdd2 712 *.VDD Delay_tile_S_i44.vdd3 713 *.GND Delay_tile_S_i44.gnd1 714 *.GND Delay_tile_S_i44.gnd3 715 *.VDD Delay_tile_S_i44.vdd4 716 *.GND Delay_tile_S_i44.gnd5 717 *.VDD Delay_tile_S_i44.vdd5 718 *.GND Delay_tile_S_i44.gnd6 719 *.IN Delay_tile_S_i44.input 707 *.INOUT Delay_tile_S_i44.inout4 134 *.OUT Delay_tile_S_i44.Out_to_Dff 20 *.OUT Delay_tile_S_i44.Timing 84 *.OUT Delay_tile_S_i44.output1 720 *.OUT Delay_tile_S_i44.output2 720 *.INOUT Delay_tile_S_i44.inout5 134 *.VDD Delay_tile_S_i45.vdd0 721 *.GND Delay_tile_S_i45.gnd0 722 *.VDD Delay_tile_S_i45.vdd1 723 *.GND Delay_tile_S_i45.gnd2 724 *.VDD Delay_tile_S_i45.vdd2 725 *.VDD Delay_tile_S_i45.vdd3 726 *.GND Delay_tile_S_i45.gnd1 727 *.GND Delay_tile_S_i45.gnd3 728 *.VDD Delay_tile_S_i45.vdd4 729 *.GND Delay_tile_S_i45.gnd5 730 *.VDD Delay_tile_S_i45.vdd5 731 *.GND Delay_tile_S_i45.gnd6 732 *.IN Delay_tile_S_i45.input 720 *.INOUT Delay_tile_S_i45.inout4 134 *.OUT Delay_tile_S_i45.Out_to_Dff 19 *.OUT Delay_tile_S_i45.Timing 83 *.OUT Delay_tile_S_i45.output1 733 *.OUT Delay_tile_S_i45.output2 733 *.INOUT Delay_tile_S_i45.inout5 134 *.VDD Delay_tile_S_i46.vdd0 734 *.GND Delay_tile_S_i46.gnd0 735 *.VDD Delay_tile_S_i46.vdd1 736 *.GND Delay_tile_S_i46.gnd2 737 *.VDD Delay_tile_S_i46.vdd2 738 *.VDD Delay_tile_S_i46.vdd3 739 *.GND Delay_tile_S_i46.gnd1 740 *.GND Delay_tile_S_i46.gnd3 741 *.VDD Delay_tile_S_i46.vdd4 742 *.GND Delay_tile_S_i46.gnd5 743 *.VDD Delay_tile_S_i46.vdd5 744 *.GND Delay_tile_S_i46.gnd6 745 *.IN Delay_tile_S_i46.input 733 *.INOUT Delay_tile_S_i46.inout4 134 *.OUT Delay_tile_S_i46.Out_to_Dff 18 *.OUT Delay_tile_S_i46.Timing 82 *.OUT Delay_tile_S_i46.output1 746 *.OUT Delay_tile_S_i46.output2 746 *.INOUT Delay_tile_S_i46.inout5 134 *.VDD Delay_tile_S_i47.vdd0 747 *.GND Delay_tile_S_i47.gnd0 748 *.VDD Delay_tile_S_i47.vdd1 749 *.GND Delay_tile_S_i47.gnd2 750 *.VDD Delay_tile_S_i47.vdd2 751 *.VDD Delay_tile_S_i47.vdd3 752 *.GND Delay_tile_S_i47.gnd1 753 *.GND Delay_tile_S_i47.gnd3 754 *.VDD Delay_tile_S_i47.vdd4 755 *.GND Delay_tile_S_i47.gnd5 756 *.VDD Delay_tile_S_i47.vdd5 757 *.GND Delay_tile_S_i47.gnd6 758 *.IN Delay_tile_S_i47.input 746 *.INOUT Delay_tile_S_i47.inout4 134 *.OUT Delay_tile_S_i47.Out_to_Dff 17 *.OUT Delay_tile_S_i47.Timing 81 *.OUT Delay_tile_S_i47.output1 759 *.OUT Delay_tile_S_i47.output2 759 *.INOUT Delay_tile_S_i47.inout5 134 *.VDD Delay_tile_S_i48.vdd0 760 *.GND Delay_tile_S_i48.gnd0 761 *.VDD Delay_tile_S_i48.vdd1 762 *.GND Delay_tile_S_i48.gnd2 763 *.VDD Delay_tile_S_i48.vdd2 764 *.VDD Delay_tile_S_i48.vdd3 765 *.GND Delay_tile_S_i48.gnd1 766 *.GND Delay_tile_S_i48.gnd3 767 *.VDD Delay_tile_S_i48.vdd4 768 *.GND Delay_tile_S_i48.gnd5 769 *.VDD Delay_tile_S_i48.vdd5 770 *.GND Delay_tile_S_i48.gnd6 771 *.IN Delay_tile_S_i48.input 759 *.INOUT Delay_tile_S_i48.inout4 134 *.OUT Delay_tile_S_i48.Out_to_Dff 16 *.OUT Delay_tile_S_i48.Timing 80 *.OUT Delay_tile_S_i48.output1 772 *.OUT Delay_tile_S_i48.output2 772 *.INOUT Delay_tile_S_i48.inout5 134 *.VDD Delay_tile_S_i49.vdd0 773 *.GND Delay_tile_S_i49.gnd0 774 *.VDD Delay_tile_S_i49.vdd1 775 *.GND Delay_tile_S_i49.gnd2 776 *.VDD Delay_tile_S_i49.vdd2 777 *.VDD Delay_tile_S_i49.vdd3 778 *.GND Delay_tile_S_i49.gnd1 779 *.GND Delay_tile_S_i49.gnd3 780 *.VDD Delay_tile_S_i49.vdd4 781 *.GND Delay_tile_S_i49.gnd5 782 *.VDD Delay_tile_S_i49.vdd5 783 *.GND Delay_tile_S_i49.gnd6 784 *.IN Delay_tile_S_i49.input 772 *.INOUT Delay_tile_S_i49.inout4 134 *.OUT Delay_tile_S_i49.Out_to_Dff 15 *.OUT Delay_tile_S_i49.Timing 79 *.OUT Delay_tile_S_i49.output1 785 *.OUT Delay_tile_S_i49.output2 785 *.INOUT Delay_tile_S_i49.inout5 134 *.VDD Delay_tile_S_i50.vdd0 786 *.GND Delay_tile_S_i50.gnd0 787 *.VDD Delay_tile_S_i50.vdd1 788 *.GND Delay_tile_S_i50.gnd2 789 *.VDD Delay_tile_S_i50.vdd2 790 *.VDD Delay_tile_S_i50.vdd3 791 *.GND Delay_tile_S_i50.gnd1 792 *.GND Delay_tile_S_i50.gnd3 793 *.VDD Delay_tile_S_i50.vdd4 794 *.GND Delay_tile_S_i50.gnd5 795 *.VDD Delay_tile_S_i50.vdd5 796 *.GND Delay_tile_S_i50.gnd6 797 *.IN Delay_tile_S_i50.input 785 *.INOUT Delay_tile_S_i50.inout4 134 *.OUT Delay_tile_S_i50.Out_to_Dff 14 *.OUT Delay_tile_S_i50.Timing 78 *.OUT Delay_tile_S_i50.output1 798 *.OUT Delay_tile_S_i50.output2 798 *.INOUT Delay_tile_S_i50.inout5 134 *.VDD Delay_tile_S_i51.vdd0 799 *.GND Delay_tile_S_i51.gnd0 800 *.VDD Delay_tile_S_i51.vdd1 801 *.GND Delay_tile_S_i51.gnd2 802 *.VDD Delay_tile_S_i51.vdd2 803 *.VDD Delay_tile_S_i51.vdd3 804 *.GND Delay_tile_S_i51.gnd1 805 *.GND Delay_tile_S_i51.gnd3 806 *.VDD Delay_tile_S_i51.vdd4 807 *.GND Delay_tile_S_i51.gnd5 808 *.VDD Delay_tile_S_i51.vdd5 809 *.GND Delay_tile_S_i51.gnd6 810 *.IN Delay_tile_S_i51.input 798 *.INOUT Delay_tile_S_i51.inout4 134 *.OUT Delay_tile_S_i51.Out_to_Dff 13 *.OUT Delay_tile_S_i51.Timing 77 *.OUT Delay_tile_S_i51.output1 811 *.OUT Delay_tile_S_i51.output2 811 *.INOUT Delay_tile_S_i51.inout5 134 *.VDD Delay_tile_S_i52.vdd0 812 *.GND Delay_tile_S_i52.gnd0 813 *.VDD Delay_tile_S_i52.vdd1 814 *.GND Delay_tile_S_i52.gnd2 815 *.VDD Delay_tile_S_i52.vdd2 816 *.VDD Delay_tile_S_i52.vdd3 817 *.GND Delay_tile_S_i52.gnd1 818 *.GND Delay_tile_S_i52.gnd3 819 *.VDD Delay_tile_S_i52.vdd4 820 *.GND Delay_tile_S_i52.gnd5 821 *.VDD Delay_tile_S_i52.vdd5 822 *.GND Delay_tile_S_i52.gnd6 823 *.IN Delay_tile_S_i52.input 811 *.INOUT Delay_tile_S_i52.inout4 134 *.OUT Delay_tile_S_i52.Out_to_Dff 12 *.OUT Delay_tile_S_i52.Timing 76 *.OUT Delay_tile_S_i52.output1 824 *.OUT Delay_tile_S_i52.output2 824 *.INOUT Delay_tile_S_i52.inout5 134 *.VDD Delay_tile_S_i53.vdd0 825 *.GND Delay_tile_S_i53.gnd0 826 *.VDD Delay_tile_S_i53.vdd1 827 *.GND Delay_tile_S_i53.gnd2 828 *.VDD Delay_tile_S_i53.vdd2 829 *.VDD Delay_tile_S_i53.vdd3 830 *.GND Delay_tile_S_i53.gnd1 831 *.GND Delay_tile_S_i53.gnd3 832 *.VDD Delay_tile_S_i53.vdd4 833 *.GND Delay_tile_S_i53.gnd5 834 *.VDD Delay_tile_S_i53.vdd5 835 *.GND Delay_tile_S_i53.gnd6 836 *.IN Delay_tile_S_i53.input 824 *.INOUT Delay_tile_S_i53.inout4 134 *.OUT Delay_tile_S_i53.Out_to_Dff 11 *.OUT Delay_tile_S_i53.Timing 75 *.OUT Delay_tile_S_i53.output1 837 *.OUT Delay_tile_S_i53.output2 837 *.INOUT Delay_tile_S_i53.inout5 134 *.VDD Delay_tile_S_i54.vdd0 838 *.GND Delay_tile_S_i54.gnd0 839 *.VDD Delay_tile_S_i54.vdd1 840 *.GND Delay_tile_S_i54.gnd2 841 *.VDD Delay_tile_S_i54.vdd2 842 *.VDD Delay_tile_S_i54.vdd3 843 *.GND Delay_tile_S_i54.gnd1 844 *.GND Delay_tile_S_i54.gnd3 845 *.VDD Delay_tile_S_i54.vdd4 846 *.GND Delay_tile_S_i54.gnd5 847 *.VDD Delay_tile_S_i54.vdd5 848 *.GND Delay_tile_S_i54.gnd6 849 *.IN Delay_tile_S_i54.input 837 *.INOUT Delay_tile_S_i54.inout4 134 *.OUT Delay_tile_S_i54.Out_to_Dff 10 *.OUT Delay_tile_S_i54.Timing 74 *.OUT Delay_tile_S_i54.output1 850 *.OUT Delay_tile_S_i54.output2 850 *.INOUT Delay_tile_S_i54.inout5 134 *.VDD Delay_tile_S_i55.vdd0 851 *.GND Delay_tile_S_i55.gnd0 852 *.VDD Delay_tile_S_i55.vdd1 853 *.GND Delay_tile_S_i55.gnd2 854 *.VDD Delay_tile_S_i55.vdd2 855 *.VDD Delay_tile_S_i55.vdd3 856 *.GND Delay_tile_S_i55.gnd1 857 *.GND Delay_tile_S_i55.gnd3 858 *.VDD Delay_tile_S_i55.vdd4 859 *.GND Delay_tile_S_i55.gnd5 860 *.VDD Delay_tile_S_i55.vdd5 861 *.GND Delay_tile_S_i55.gnd6 862 *.IN Delay_tile_S_i55.input 850 *.INOUT Delay_tile_S_i55.inout4 134 *.OUT Delay_tile_S_i55.Out_to_Dff 9 *.OUT Delay_tile_S_i55.Timing 73 *.OUT Delay_tile_S_i55.output1 863 *.OUT Delay_tile_S_i55.output2 863 *.INOUT Delay_tile_S_i55.inout5 134 *.VDD Delay_tile_S_i56.vdd0 864 *.GND Delay_tile_S_i56.gnd0 865 *.VDD Delay_tile_S_i56.vdd1 866 *.GND Delay_tile_S_i56.gnd2 867 *.VDD Delay_tile_S_i56.vdd2 868 *.VDD Delay_tile_S_i56.vdd3 869 *.GND Delay_tile_S_i56.gnd1 870 *.GND Delay_tile_S_i56.gnd3 871 *.VDD Delay_tile_S_i56.vdd4 872 *.GND Delay_tile_S_i56.gnd5 873 *.VDD Delay_tile_S_i56.vdd5 874 *.GND Delay_tile_S_i56.gnd6 875 *.IN Delay_tile_S_i56.input 863 *.INOUT Delay_tile_S_i56.inout4 134 *.OUT Delay_tile_S_i56.Out_to_Dff 8 *.OUT Delay_tile_S_i56.Timing 72 *.OUT Delay_tile_S_i56.output1 876 *.OUT Delay_tile_S_i56.output2 876 *.INOUT Delay_tile_S_i56.inout5 134 *.VDD Delay_tile_S_i57.vdd0 877 *.GND Delay_tile_S_i57.gnd0 878 *.VDD Delay_tile_S_i57.vdd1 879 *.GND Delay_tile_S_i57.gnd2 880 *.VDD Delay_tile_S_i57.vdd2 881 *.VDD Delay_tile_S_i57.vdd3 882 *.GND Delay_tile_S_i57.gnd1 883 *.GND Delay_tile_S_i57.gnd3 884 *.VDD Delay_tile_S_i57.vdd4 885 *.GND Delay_tile_S_i57.gnd5 886 *.VDD Delay_tile_S_i57.vdd5 887 *.GND Delay_tile_S_i57.gnd6 888 *.IN Delay_tile_S_i57.input 876 *.INOUT Delay_tile_S_i57.inout4 134 *.OUT Delay_tile_S_i57.Out_to_Dff 7 *.OUT Delay_tile_S_i57.Timing 71 *.OUT Delay_tile_S_i57.output1 889 *.OUT Delay_tile_S_i57.output2 889 *.INOUT Delay_tile_S_i57.inout5 134 *.VDD Delay_tile_S_i58.vdd0 890 *.GND Delay_tile_S_i58.gnd0 891 *.VDD Delay_tile_S_i58.vdd1 892 *.GND Delay_tile_S_i58.gnd2 893 *.VDD Delay_tile_S_i58.vdd2 894 *.VDD Delay_tile_S_i58.vdd3 895 *.GND Delay_tile_S_i58.gnd1 896 *.GND Delay_tile_S_i58.gnd3 897 *.VDD Delay_tile_S_i58.vdd4 898 *.GND Delay_tile_S_i58.gnd5 899 *.VDD Delay_tile_S_i58.vdd5 900 *.GND Delay_tile_S_i58.gnd6 901 *.IN Delay_tile_S_i58.input 889 *.INOUT Delay_tile_S_i58.inout4 134 *.OUT Delay_tile_S_i58.Out_to_Dff 6 *.OUT Delay_tile_S_i58.Timing 70 *.OUT Delay_tile_S_i58.output1 902 *.OUT Delay_tile_S_i58.output2 902 *.INOUT Delay_tile_S_i58.inout5 134 *.VDD Delay_tile_S_i59.vdd0 903 *.GND Delay_tile_S_i59.gnd0 904 *.VDD Delay_tile_S_i59.vdd1 905 *.GND Delay_tile_S_i59.gnd2 906 *.VDD Delay_tile_S_i59.vdd2 907 *.VDD Delay_tile_S_i59.vdd3 908 *.GND Delay_tile_S_i59.gnd1 909 *.GND Delay_tile_S_i59.gnd3 910 *.VDD Delay_tile_S_i59.vdd4 911 *.GND Delay_tile_S_i59.gnd5 912 *.VDD Delay_tile_S_i59.vdd5 913 *.GND Delay_tile_S_i59.gnd6 914 *.IN Delay_tile_S_i59.input 902 *.INOUT Delay_tile_S_i59.inout4 134 *.OUT Delay_tile_S_i59.Out_to_Dff 5 *.OUT Delay_tile_S_i59.Timing 69 *.OUT Delay_tile_S_i59.output1 915 *.OUT Delay_tile_S_i59.output2 915 *.INOUT Delay_tile_S_i59.inout5 134 *.VDD Delay_tile_S_i60.vdd0 916 *.GND Delay_tile_S_i60.gnd0 917 *.VDD Delay_tile_S_i60.vdd1 918 *.GND Delay_tile_S_i60.gnd2 919 *.VDD Delay_tile_S_i60.vdd2 920 *.VDD Delay_tile_S_i60.vdd3 921 *.GND Delay_tile_S_i60.gnd1 922 *.GND Delay_tile_S_i60.gnd3 923 *.VDD Delay_tile_S_i60.vdd4 924 *.GND Delay_tile_S_i60.gnd5 925 *.VDD Delay_tile_S_i60.vdd5 926 *.GND Delay_tile_S_i60.gnd6 927 *.IN Delay_tile_S_i60.input 915 *.INOUT Delay_tile_S_i60.inout4 134 *.OUT Delay_tile_S_i60.Out_to_Dff 4 *.OUT Delay_tile_S_i60.Timing 68 *.OUT Delay_tile_S_i60.output1 928 *.OUT Delay_tile_S_i60.output2 928 *.INOUT Delay_tile_S_i60.inout5 134 *.VDD Delay_tile_S_i61.vdd0 929 *.GND Delay_tile_S_i61.gnd0 930 *.VDD Delay_tile_S_i61.vdd1 931 *.GND Delay_tile_S_i61.gnd2 932 *.VDD Delay_tile_S_i61.vdd2 933 *.VDD Delay_tile_S_i61.vdd3 934 *.GND Delay_tile_S_i61.gnd1 935 *.GND Delay_tile_S_i61.gnd3 936 *.VDD Delay_tile_S_i61.vdd4 937 *.GND Delay_tile_S_i61.gnd5 938 *.VDD Delay_tile_S_i61.vdd5 939 *.GND Delay_tile_S_i61.gnd6 940 *.IN Delay_tile_S_i61.input 928 *.INOUT Delay_tile_S_i61.inout4 134 *.OUT Delay_tile_S_i61.Out_to_Dff 3 *.OUT Delay_tile_S_i61.Timing 67 *.OUT Delay_tile_S_i61.output1 941 *.OUT Delay_tile_S_i61.output2 941 *.INOUT Delay_tile_S_i61.inout5 134 *.VDD Delay_tile_S_i62.vdd0 942 *.GND Delay_tile_S_i62.gnd0 943 *.VDD Delay_tile_S_i62.vdd1 944 *.GND Delay_tile_S_i62.gnd2 945 *.VDD Delay_tile_S_i62.vdd2 946 *.VDD Delay_tile_S_i62.vdd3 947 *.GND Delay_tile_S_i62.gnd1 948 *.GND Delay_tile_S_i62.gnd3 949 *.VDD Delay_tile_S_i62.vdd4 950 *.GND Delay_tile_S_i62.gnd5 951 *.VDD Delay_tile_S_i62.vdd5 952 *.GND Delay_tile_S_i62.gnd6 953 *.IN Delay_tile_S_i62.input 941 *.INOUT Delay_tile_S_i62.inout4 134 *.OUT Delay_tile_S_i62.Out_to_Dff 2 *.OUT Delay_tile_S_i62.Timing 66 *.OUT Delay_tile_S_i62.output1 954 *.OUT Delay_tile_S_i62.output2 954 *.INOUT Delay_tile_S_i62.inout5 134 *.VDD Delay_tile_S_i63.vdd0 955 *.GND Delay_tile_S_i63.gnd0 956 *.VDD Delay_tile_S_i63.vdd1 957 *.GND Delay_tile_S_i63.gnd2 958 *.VDD Delay_tile_S_i63.vdd2 959 *.VDD Delay_tile_S_i63.vdd3 960 *.GND Delay_tile_S_i63.gnd1 961 *.GND Delay_tile_S_i63.gnd3 962 *.VDD Delay_tile_S_i63.vdd4 963 *.GND Delay_tile_S_i63.gnd5 964 *.VDD Delay_tile_S_i63.vdd5 965 *.GND Delay_tile_S_i63.gnd6 966 *.IN Delay_tile_S_i63.input 954 *.INOUT Delay_tile_S_i63.inout4 134 *.OUT Delay_tile_S_i63.Out_to_Dff 1 *.OUT Delay_tile_S_i63.Timing 65 *.OUT Delay_tile_S_i63.output1 967 *.OUT Delay_tile_S_i63.output2 967 *.INOUT Delay_tile_S_i63.inout5 134 *.VDD Delay_Bal_S_i0.vdd0 968 *.GND Delay_Bal_S_i0.gnd0 969 *.IN Delay_Bal_S_i0.input 131 *.IN Delay_Bal_S_i0.Delay_control 134 *.OUT Delay_Bal_S_i0.Out_to_Phase 132 *.GND Delay_Bal_S_i0.gnd1 970 *.VDD Delay_Bal_S_i0.vdd1 971 *.INOUT Delay_Bal_S_i0.control 134 *.VDD Delay_Bal_S_i1.vdd0 972 *.GND Delay_Bal_S_i1.gnd0 973 *.IN Delay_Bal_S_i1.input 967 *.IN Delay_Bal_S_i1.Delay_control 134 *.OUT Delay_Bal_S_i1.Out_to_Phase 135 *.GND Delay_Bal_S_i1.gnd1 974 *.VDD Delay_Bal_S_i1.vdd1 975 *.INOUT Delay_Bal_S_i1.control 134 *.GND Phase_S_i0.gnd0 976 *.VDD Phase_S_i0.vdd0 977 *.IN Phase_S_i0.Phase_B 135 *.IN Phase_S_i0.Phase_a 132 *.VDD Phase_S_i0.vdd1 978 *.GND Phase_S_i0.gnd1 979 *.GND Phase_S_i0.gnd2 980 *.VDD Phase_S_i0.vdd3 981 *.VDD Phase_S_i0.vdd2 982 *.VDD Phase_S_i0.vdd4 983 *.GND Phase_S_i0.gnd3 984 *.VDD Phase_S_i0.vdd5 985 *.GND Phase_S_i0.gnd4 986 *.GND Phase_S_i0.gnd5 987 *.VDD Phase_S_i0.vdd6 988 *.GND Phase_S_i0.gnd7 989 *.VDD Phase_S_i0.vdd7 990 *.GND Phase_S_i0.gnd8 991 *.GND Phase_S_i0.gnd6 992 *.VDD Phase_S_i0.vdd9 993 *.VDD Phase_S_i0.vdd8 994 *.IN Phase_S_i0.RESET 133 *.INOUT Phase_S_i0.cap_volt 134 *.OUT Phase_S_i0.Ph_Cntrl_L 134 *.OUT Phase_S_i0.Ph_Cntrl_R 134 *.IN Phase_S_i0.Phase_B_M1 135 *.GND Phi_Driver_S_i0.gnd0 995 *.GND Phi_Driver_S_i0.gnd1 996 *.VDD Phi_Driver_S_i0.vdd3 997 *.VDD Phi_Driver_S_i0.vdd4 998 *.OUT Phi_Driver_S_i0.To_Channels 129 *.OUT Phi_Driver_S_i0.To_Delay 131 *.IN Phi_Driver_S_i0.PHI_in 130 *.Vnwell 1335 0 5 *.Vbulk 1334 0 0 *.Vpwell 1336 0 0 *.Vbulk 1334 0 5 VVDD0 136 0 5.00 VGND0 137 0 0 VVDD1 138 0 5.00 VGND1 139 0 0 VVDD2 140 0 5.00 VVDD3 141 0 5.00 VGND2 142 0 0 VGND3 143 0 0 VVDD4 144 0 5.00 VGND4 145 0 0 VVDD5 146 0 5.00 VGND5 147 0 0 VVDD6 149 0 5.00 VGND6 150 0 0 VVDD7 151 0 5.00 VGND7 152 0 0 VVDD8 153 0 5.00 VVDD9 154 0 5.00 VGND8 155 0 0 VGND9 156 0 0 VVDD10 157 0 5.00 VGND10 158 0 0 VVDD11 159 0 5.00 VGND11 160 0 0 VVDD12 162 0 5.00 VGND12 163 0 0 VVDD13 164 0 5.00 VGND13 165 0 0 VVDD14 166 0 5.00 VVDD15 167 0 5.00 VGND14 168 0 0 VGND15 169 0 0 VVDD16 170 0 5.00 VGND16 171 0 0 VVDD17 172 0 5.00 VGND17 173 0 0 VVDD18 175 0 5.00 VGND18 176 0 0 VVDD19 177 0 5.00 VGND19 178 0 0 VVDD20 179 0 5.00 VVDD21 180 0 5.00 VGND20 181 0 0 VGND21 182 0 0 VVDD22 183 0 5.00 VGND22 184 0 0 VVDD23 185 0 5.00 VGND23 186 0 0 VVDD24 188 0 5.00 VGND24 189 0 0 VVDD25 190 0 5.00 VGND25 191 0 0 VVDD26 192 0 5.00 VVDD27 193 0 5.00 VGND26 194 0 0 VGND27 195 0 0 VVDD28 196 0 5.00 VGND28 197 0 0 VVDD29 198 0 5.00 VGND29 199 0 0 VVDD30 201 0 5.00 VGND30 202 0 0 VVDD31 203 0 5.00 VGND31 204 0 0 VVDD32 205 0 5.00 VVDD33 206 0 5.00 VGND32 207 0 0 VGND33 208 0 0 VVDD34 209 0 5.00 VGND34 210 0 0 VVDD35 211 0 5.00 VGND35 212 0 0 VVDD36 214 0 5.00 VGND36 215 0 0 VVDD37 216 0 5.00 VGND37 217 0 0 VVDD38 218 0 5.00 VVDD39 219 0 5.00 VGND38 220 0 0 VGND39 221 0 0 VVDD40 222 0 5.00 VGND40 223 0 0 VVDD41 224 0 5.00 VGND41 225 0 0 VVDD42 227 0 5.00 VGND42 228 0 0 VVDD43 229 0 5.00 VGND43 230 0 0 VVDD44 231 0 5.00 VVDD45 232 0 5.00 VGND44 233 0 0 VGND45 234 0 0 VVDD46 235 0 5.00 VGND46 236 0 0 VVDD47 237 0 5.00 VGND47 238 0 0 VVDD48 240 0 5.00 VGND48 241 0 0 VVDD49 242 0 5.00 VGND49 243 0 0 VVDD50 244 0 5.00 VVDD51 245 0 5.00 VGND50 246 0 0 VGND51 247 0 0 VVDD52 248 0 5.00 VGND52 249 0 0 VVDD53 250 0 5.00 VGND53 251 0 0 VVDD54 253 0 5.00 VGND54 254 0 0 VVDD55 255 0 5.00 VGND55 256 0 0 VVDD56 257 0 5.00 VVDD57 258 0 5.00 VGND56 259 0 0 VGND57 260 0 0 VVDD58 261 0 5.00 VGND58 262 0 0 VVDD59 263 0 5.00 VGND59 264 0 0 VVDD60 266 0 5.00 VGND60 267 0 0 VVDD61 268 0 5.00 VGND61 269 0 0 VVDD62 270 0 5.00 VVDD63 271 0 5.00 VGND62 272 0 0 VGND63 273 0 0 VVDD64 274 0 5.00 VGND64 275 0 0 VVDD65 276 0 5.00 VGND65 277 0 0 VVDD66 279 0 5.00 VGND66 280 0 0 VVDD67 281 0 5.00 VGND67 282 0 0 VVDD68 283 0 5.00 VVDD69 284 0 5.00 VGND68 285 0 0 VGND69 286 0 0 VVDD70 287 0 5.00 VGND70 288 0 0 VVDD71 289 0 5.00 VGND71 290 0 0 VVDD72 292 0 5.00 VGND72 293 0 0 VVDD73 294 0 5.00 VGND73 295 0 0 VVDD74 296 0 5.00 VVDD75 297 0 5.00 VGND74 298 0 0 VGND75 299 0 0 VVDD76 300 0 5.00 VGND76 301 0 0 VVDD77 302 0 5.00 VGND77 303 0 0 VVDD78 305 0 5.00 VGND78 306 0 0 VVDD79 307 0 5.00 VGND79 308 0 0 VVDD80 309 0 5.00 VVDD81 310 0 5.00 VGND80 311 0 0 VGND81 312 0 0 VVDD82 313 0 5.00 VGND82 314 0 0 VVDD83 315 0 5.00 VGND83 316 0 0 VVDD84 318 0 5.00 VGND84 319 0 0 VVDD85 320 0 5.00 VGND85 321 0 0 VVDD86 322 0 5.00 VVDD87 323 0 5.00 VGND86 324 0 0 VGND87 325 0 0 VVDD88 326 0 5.00 VGND88 327 0 0 VVDD89 328 0 5.00 VGND89 329 0 0 VVDD90 331 0 5.00 VGND90 332 0 0 VVDD91 333 0 5.00 VGND91 334 0 0 VVDD92 335 0 5.00 VVDD93 336 0 5.00 VGND92 337 0 0 VGND93 338 0 0 VVDD94 339 0 5.00 VGND94 340 0 0 VVDD95 341 0 5.00 VGND95 342 0 0 VVDD96 344 0 5.00 VGND96 345 0 0 VVDD97 346 0 5.00 VGND97 347 0 0 VVDD98 348 0 5.00 VVDD99 349 0 5.00 VGND98 350 0 0 VGND99 351 0 0 VVDD100 352 0 5.00 VGND100 353 0 0 VVDD101 354 0 5.00 VGND101 355 0 0 VVDD102 357 0 5.00 VGND102 358 0 0 VVDD103 359 0 5.00 VGND103 360 0 0 VVDD104 361 0 5.00 VVDD105 362 0 5.00 VGND104 363 0 0 VGND105 364 0 0 VVDD106 365 0 5.00 VGND106 366 0 0 VVDD107 367 0 5.00 VGND107 368 0 0 VVDD108 370 0 5.00 VGND108 371 0 0 VVDD109 372 0 5.00 VGND109 373 0 0 VVDD110 374 0 5.00 VVDD111 375 0 5.00 VGND110 376 0 0 VGND111 377 0 0 VVDD112 378 0 5.00 VGND112 379 0 0 VVDD113 380 0 5.00 VGND113 381 0 0 VVDD114 383 0 5.00 VGND114 384 0 0 VVDD115 385 0 5.00 VGND115 386 0 0 VVDD116 387 0 5.00 VVDD117 388 0 5.00 VGND116 389 0 0 VGND117 390 0 0 VVDD118 391 0 5.00 VGND118 392 0 0 VVDD119 393 0 5.00 VGND119 394 0 0 VVDD120 396 0 5.00 VGND120 397 0 0 VVDD121 398 0 5.00 VGND121 399 0 0 VVDD122 400 0 5.00 VVDD123 401 0 5.00 VGND122 402 0 0 VGND123 403 0 0 VVDD124 404 0 5.00 VGND124 405 0 0 VVDD125 406 0 5.00 VGND125 407 0 0 VVDD126 409 0 5.00 VGND126 410 0 0 VVDD127 411 0 5.00 VGND127 412 0 0 VVDD128 413 0 5.00 VVDD129 414 0 5.00 VGND128 415 0 0 VGND129 416 0 0 VVDD130 417 0 5.00 VGND130 418 0 0 VVDD131 419 0 5.00 VGND131 420 0 0 VVDD132 422 0 5.00 VGND132 423 0 0 VVDD133 424 0 5.00 VGND133 425 0 0 VVDD134 426 0 5.00 VVDD135 427 0 5.00 VGND134 428 0 0 VGND135 429 0 0 VVDD136 430 0 5.00 VGND136 431 0 0 VVDD137 432 0 5.00 VGND137 433 0 0 VVDD138 435 0 5.00 VGND138 436 0 0 VVDD139 437 0 5.00 VGND139 438 0 0 VVDD140 439 0 5.00 VVDD141 440 0 5.00 VGND140 441 0 0 VGND141 442 0 0 VVDD142 443 0 5.00 VGND142 444 0 0 VVDD143 445 0 5.00 VGND143 446 0 0 VVDD144 448 0 5.00 VGND144 449 0 0 VVDD145 450 0 5.00 VGND145 451 0 0 VVDD146 452 0 5.00 VVDD147 453 0 5.00 VGND146 454 0 0 VGND147 455 0 0 VVDD148 456 0 5.00 VGND148 457 0 0 VVDD149 458 0 5.00 VGND149 459 0 0 VVDD150 461 0 5.00 VGND150 462 0 0 VVDD151 463 0 5.00 VGND151 464 0 0 VVDD152 465 0 5.00 VVDD153 466 0 5.00 VGND152 467 0 0 VGND153 468 0 0 VVDD154 469 0 5.00 VGND154 470 0 0 VVDD155 471 0 5.00 VGND155 472 0 0 VVDD156 474 0 5.00 VGND156 475 0 0 VVDD157 476 0 5.00 VGND157 477 0 0 VVDD158 478 0 5.00 VVDD159 479 0 5.00 VGND158 480 0 0 VGND159 481 0 0 VVDD160 482 0 5.00 VGND160 483 0 0 VVDD161 484 0 5.00 VGND161 485 0 0 VVDD162 487 0 5.00 VGND162 488 0 0 VVDD163 489 0 5.00 VGND163 490 0 0 VVDD164 491 0 5.00 VVDD165 492 0 5.00 VGND164 493 0 0 VGND165 494 0 0 VVDD166 495 0 5.00 VGND166 496 0 0 VVDD167 497 0 5.00 VGND167 498 0 0 VVDD168 500 0 5.00 VGND168 501 0 0 VVDD169 502 0 5.00 VGND169 503 0 0 VVDD170 504 0 5.00 VVDD171 505 0 5.00 VGND170 506 0 0 VGND171 507 0 0 VVDD172 508 0 5.00 VGND172 509 0 0 VVDD173 510 0 5.00 VGND173 511 0 0 VVDD174 513 0 5.00 VGND174 514 0 0 VVDD175 515 0 5.00 VGND175 516 0 0 VVDD176 517 0 5.00 VVDD177 518 0 5.00 VGND176 519 0 0 VGND177 520 0 0 VVDD178 521 0 5.00 VGND178 522 0 0 VVDD179 523 0 5.00 VGND179 524 0 0 VVDD180 526 0 5.00 VGND180 527 0 0 VVDD181 528 0 5.00 VGND181 529 0 0 VVDD182 530 0 5.00 VVDD183 531 0 5.00 VGND182 532 0 0 VGND183 533 0 0 VVDD184 534 0 5.00 VGND184 535 0 0 VVDD185 536 0 5.00 VGND185 537 0 0 VVDD186 539 0 5.00 VGND186 540 0 0 VVDD187 541 0 5.00 VGND187 542 0 0 VVDD188 543 0 5.00 VVDD189 544 0 5.00 VGND188 545 0 0 VGND189 546 0 0 VVDD190 547 0 5.00 VGND190 548 0 0 VVDD191 549 0 5.00 VGND191 550 0 0 VVDD192 552 0 5.00 VGND192 553 0 0 VVDD193 554 0 5.00 VGND193 555 0 0 VVDD194 556 0 5.00 VVDD195 557 0 5.00 VGND194 558 0 0 VGND195 559 0 0 VVDD196 560 0 5.00 VGND196 561 0 0 VVDD197 562 0 5.00 VGND197 563 0 0 VVDD198 565 0 5.00 VGND198 566 0 0 VVDD199 567 0 5.00 VGND199 568 0 0 VVDD200 569 0 5.00 VVDD201 570 0 5.00 VGND200 571 0 0 VGND201 572 0 0 VVDD202 573 0 5.00 VGND202 574 0 0 VVDD203 575 0 5.00 VGND203 576 0 0 VVDD204 578 0 5.00 VGND204 579 0 0 VVDD205 580 0 5.00 VGND205 581 0 0 VVDD206 582 0 5.00 VVDD207 583 0 5.00 VGND206 584 0 0 VGND207 585 0 0 VVDD208 586 0 5.00 VGND208 587 0 0 VVDD209 588 0 5.00 VGND209 589 0 0 VVDD210 591 0 5.00 VGND210 592 0 0 VVDD211 593 0 5.00 VGND211 594 0 0 VVDD212 595 0 5.00 VVDD213 596 0 5.00 VGND212 597 0 0 VGND213 598 0 0 VVDD214 599 0 5.00 VGND214 600 0 0 VVDD215 601 0 5.00 VGND215 602 0 0 VVDD216 604 0 5.00 VGND216 605 0 0 VVDD217 606 0 5.00 VGND217 607 0 0 VVDD218 608 0 5.00 VVDD219 609 0 5.00 VGND218 610 0 0 VGND219 611 0 0 VVDD220 612 0 5.00 VGND220 613 0 0 VVDD221 614 0 5.00 VGND221 615 0 0 VVDD222 617 0 5.00 VGND222 618 0 0 VVDD223 619 0 5.00 VGND223 620 0 0 VVDD224 621 0 5.00 VVDD225 622 0 5.00 VGND224 623 0 0 VGND225 624 0 0 VVDD226 625 0 5.00 VGND226 626 0 0 VVDD227 627 0 5.00 VGND227 628 0 0 VVDD228 630 0 5.00 VGND228 631 0 0 VVDD229 632 0 5.00 VGND229 633 0 0 VVDD230 634 0 5.00 VVDD231 635 0 5.00 VGND230 636 0 0 VGND231 637 0 0 VVDD232 638 0 5.00 VGND232 639 0 0 VVDD233 640 0 5.00 VGND233 641 0 0 VVDD234 643 0 5.00 VGND234 644 0 0 VVDD235 645 0 5.00 VGND235 646 0 0 VVDD236 647 0 5.00 VVDD237 648 0 5.00 VGND236 649 0 0 VGND237 650 0 0 VVDD238 651 0 5.00 VGND238 652 0 0 VVDD239 653 0 5.00 VGND239 654 0 0 VVDD240 656 0 5.00 VGND240 657 0 0 VVDD241 658 0 5.00 VGND241 659 0 0 VVDD242 660 0 5.00 VVDD243 661 0 5.00 VGND242 662 0 0 VGND243 663 0 0 VVDD244 664 0 5.00 VGND244 665 0 0 VVDD245 666 0 5.00 VGND245 667 0 0 VVDD246 669 0 5.00 VGND246 670 0 0 VVDD247 671 0 5.00 VGND247 672 0 0 VVDD248 673 0 5.00 VVDD249 674 0 5.00 VGND248 675 0 0 VGND249 676 0 0 VVDD250 677 0 5.00 VGND250 678 0 0 VVDD251 679 0 5.00 VGND251 680 0 0 VVDD252 682 0 5.00 VGND252 683 0 0 VVDD253 684 0 5.00 VGND253 685 0 0 VVDD254 686 0 5.00 VVDD255 687 0 5.00 VGND254 688 0 0 VGND255 689 0 0 VVDD256 690 0 5.00 VGND256 691 0 0 VVDD257 692 0 5.00 VGND257 693 0 0 VVDD258 695 0 5.00 VGND258 696 0 0 VVDD259 697 0 5.00 VGND259 698 0 0 VVDD260 699 0 5.00 VVDD261 700 0 5.00 VGND260 701 0 0 VGND261 702 0 0 VVDD262 703 0 5.00 VGND262 704 0 0 VVDD263 705 0 5.00 VGND263 706 0 0 VVDD264 708 0 5.00 VGND264 709 0 0 VVDD265 710 0 5.00 VGND265 711 0 0 VVDD266 712 0 5.00 VVDD267 713 0 5.00 VGND266 714 0 0 VGND267 715 0 0 VVDD268 716 0 5.00 VGND268 717 0 0 VVDD269 718 0 5.00 VGND269 719 0 0 VVDD270 721 0 5.00 VGND270 722 0 0 VVDD271 723 0 5.00 VGND271 724 0 0 VVDD272 725 0 5.00 VVDD273 726 0 5.00 VGND272 727 0 0 VGND273 728 0 0 VVDD274 729 0 5.00 VGND274 730 0 0 VVDD275 731 0 5.00 VGND275 732 0 0 VVDD276 734 0 5.00 VGND276 735 0 0 VVDD277 736 0 5.00 VGND277 737 0 0 VVDD278 738 0 5.00 VVDD279 739 0 5.00 VGND278 740 0 0 VGND279 741 0 0 VVDD280 742 0 5.00 VGND280 743 0 0 VVDD281 744 0 5.00 VGND281 745 0 0 VVDD282 747 0 5.00 VGND282 748 0 0 VVDD283 749 0 5.00 VGND283 750 0 0 VVDD284 751 0 5.00 VVDD285 752 0 5.00 VGND284 753 0 0 VGND285 754 0 0 VVDD286 755 0 5.00 VGND286 756 0 0 VVDD287 757 0 5.00 VGND287 758 0 0 VVDD288 760 0 5.00 VGND288 761 0 0 VVDD289 762 0 5.00 VGND289 763 0 0 VVDD290 764 0 5.00 VVDD291 765 0 5.00 VGND290 766 0 0 VGND291 767 0 0 VVDD292 768 0 5.00 VGND292 769 0 0 VVDD293 770 0 5.00 VGND293 771 0 0 VVDD294 773 0 5.00 VGND294 774 0 0 VVDD295 775 0 5.00 VGND295 776 0 0 VVDD296 777 0 5.00 VVDD297 778 0 5.00 VGND296 779 0 0 VGND297 780 0 0 VVDD298 781 0 5.00 VGND298 782 0 0 VVDD299 783 0 5.00 VGND299 784 0 0 VVDD300 786 0 5.00 VGND300 787 0 0 VVDD301 788 0 5.00 VGND301 789 0 0 VVDD302 790 0 5.00 VVDD303 791 0 5.00 VGND302 792 0 0 VGND303 793 0 0 VVDD304 794 0 5.00 VGND304 795 0 0 VVDD305 796 0 5.00 VGND305 797 0 0 VVDD306 799 0 5.00 VGND306 800 0 0 VVDD307 801 0 5.00 VGND307 802 0 0 VVDD308 803 0 5.00 VVDD309 804 0 5.00 VGND308 805 0 0 VGND309 806 0 0 VVDD310 807 0 5.00 VGND310 808 0 0 VVDD311 809 0 5.00 VGND311 810 0 0 VVDD312 812 0 5.00 VGND312 813 0 0 VVDD313 814 0 5.00 VGND313 815 0 0 VVDD314 816 0 5.00 VVDD315 817 0 5.00 VGND314 818 0 0 VGND315 819 0 0 VVDD316 820 0 5.00 VGND316 821 0 0 VVDD317 822 0 5.00 VGND317 823 0 0 VVDD318 825 0 5.00 VGND318 826 0 0 VVDD319 827 0 5.00 VGND319 828 0 0 VVDD320 829 0 5.00 VVDD321 830 0 5.00 VGND320 831 0 0 VGND321 832 0 0 VVDD322 833 0 5.00 VGND322 834 0 0 VVDD323 835 0 5.00 VGND323 836 0 0 VVDD324 838 0 5.00 VGND324 839 0 0 VVDD325 840 0 5.00 VGND325 841 0 0 VVDD326 842 0 5.00 VVDD327 843 0 5.00 VGND326 844 0 0 VGND327 845 0 0 VVDD328 846 0 5.00 VGND328 847 0 0 VVDD329 848 0 5.00 VGND329 849 0 0 VVDD330 851 0 5.00 VGND330 852 0 0 VVDD331 853 0 5.00 VGND331 854 0 0 VVDD332 855 0 5.00 VVDD333 856 0 5.00 VGND332 857 0 0 VGND333 858 0 0 VVDD334 859 0 5.00 VGND334 860 0 0 VVDD335 861 0 5.00 VGND335 862 0 0 VVDD336 864 0 5.00 VGND336 865 0 0 VVDD337 866 0 5.00 VGND337 867 0 0 VVDD338 868 0 5.00 VVDD339 869 0 5.00 VGND338 870 0 0 VGND339 871 0 0 VVDD340 872 0 5.00 VGND340 873 0 0 VVDD341 874 0 5.00 VGND341 875 0 0 VVDD342 877 0 5.00 VGND342 878 0 0 VVDD343 879 0 5.00 VGND343 880 0 0 VVDD344 881 0 5.00 VVDD345 882 0 5.00 VGND344 883 0 0 VGND345 884 0 0 VVDD346 885 0 5.00 VGND346 886 0 0 VVDD347 887 0 5.00 VGND347 888 0 0 VVDD348 890 0 5.00 VGND348 891 0 0 VVDD349 892 0 5.00 VGND349 893 0 0 VVDD350 894 0 5.00 VVDD351 895 0 5.00 VGND350 896 0 0 VGND351 897 0 0 VVDD352 898 0 5.00 VGND352 899 0 0 VVDD353 900 0 5.00 VGND353 901 0 0 VVDD354 903 0 5.00 VGND354 904 0 0 VVDD355 905 0 5.00 VGND355 906 0 0 VVDD356 907 0 5.00 VVDD357 908 0 5.00 VGND356 909 0 0 VGND357 910 0 0 VVDD358 911 0 5.00 VGND358 912 0 0 VVDD359 913 0 5.00 VGND359 914 0 0 VVDD360 916 0 5.00 VGND360 917 0 0 VVDD361 918 0 5.00 VGND361 919 0 0 VVDD362 920 0 5.00 VVDD363 921 0 5.00 VGND362 922 0 0 VGND363 923 0 0 VVDD364 924 0 5.00 VGND364 925 0 0 VVDD365 926 0 5.00 VGND365 927 0 0 VVDD366 929 0 5.00 VGND366 930 0 0 VVDD367 931 0 5.00 VGND367 932 0 0 VVDD368 933 0 5.00 VVDD369 934 0 5.00 VGND368 935 0 0 VGND369 936 0 0 VVDD370 937 0 5.00 VGND370 938 0 0 VVDD371 939 0 5.00 VGND371 940 0 0 VVDD372 942 0 5.00 VGND372 943 0 0 VVDD373 944 0 5.00 VGND373 945 0 0 VVDD374 946 0 5.00 VVDD375 947 0 5.00 VGND374 948 0 0 VGND375 949 0 0 VVDD376 950 0 5.00 VGND376 951 0 0 VVDD377 952 0 5.00 VGND377 953 0 0 VVDD378 955 0 5.00 VGND378 956 0 0 VVDD379 957 0 5.00 VGND379 958 0 0 VVDD380 959 0 5.00 VVDD381 960 0 5.00 VGND380 961 0 0 VGND381 962 0 0 VVDD382 963 0 5.00 VGND382 964 0 0 VVDD383 965 0 5.00 VGND383 966 0 0 VVDD384 968 0 5.00 VGND384 969 0 0 VGND385 970 0 0 VVDD385 971 0 5.00 VVDD386 972 0 5.00 VGND386 973 0 0 VGND387 974 0 0 VVDD387 975 0 5.00 VGND388 976 0 0 VVDD388 977 0 5.00 VVDD389 978 0 5.00 VGND389 979 0 0 VGND390 980 0 0 VVDD390 981 0 5.00 VVDD391 982 0 5.00 VVDD392 983 0 5.00 VGND391 984 0 0 VVDD393 985 0 5.00 VGND392 986 0 0 VGND393 987 0 0 VVDD394 988 0 5.00 VGND394 989 0 0 VVDD395 990 0 5.00 VGND395 991 0 0 VGND396 992 0 0 VVDD396 993 0 5.00 VVDD397 994 0 5.00 VGND397 995 0 0 VGND398 996 0 0 VVDD398 997 0 5.00 VVDD399 998 0 5.00 *TEXT Out_to_Dff[63] " "; *TEXT node0[7] " "; *TEXT node1[7] " "; *TEXT node2[7] " "; *TEXT node3[7] " "; *TEXT node4[7] " "; *TEXT node5[7] " "; *TEXT node6[7] " "; *TEXT node7[7] " "; *TEXT Timing[63] " "; *TEXT node64[7] " "; *TEXT node65[7] " "; *TEXT node66[7] " "; *TEXT node67[7] " "; *TEXT node68[7] " "; *TEXT node69[7] " "; *TEXT node70[7] " "; *TEXT node71[7] " "; *TEXT w22.[1][0] "7:0"; *TEXT w31.[2][50] "15:8"; *TEXT w53.[2][50] "23:16"; *TEXT w55.[2][50] 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w130.[1][0] "2"; *TEXT w131.[1][0] "3"; *TEXT w132.[1][0] "4"; *TEXT w133.[1][0] "5"; *TEXT w134.[1][0] "6"; *TEXT w135.[1][0] "7"; *TEXT w136.[1][0] "0"; *TEXT w138.[1][0] "1"; *TEXT w140.[1][0] "2"; *TEXT w142.[1][0] "3"; *TEXT w144.[1][0] "4"; *TEXT w146.[1][0] "5"; *TEXT w148.[1][0] "6"; *TEXT w150.[1][0] "7"; *TEXT w152.[1][0] "0"; *TEXT w153.[1][0] "1"; *TEXT w154.[1][0] "2"; *TEXT w155.[1][0] "3"; *TEXT w156.[1][0] "4"; *TEXT w157.[1][0] "5"; *TEXT w158.[1][0] "6"; *TEXT w159.[1][0] "7"; *TEXT w160.[1][0] "0"; *TEXT w162.[1][0] "1"; *TEXT w164.[1][0] "2"; *TEXT w166.[1][0] "3"; *TEXT w168.[1][0] "4"; *TEXT w170.[1][0] "5"; *TEXT w172.[1][0] "6"; *TEXT w174.[1][0] "7"; *TEXT w176.[1][0] "0"; *TEXT w177.[1][0] "1"; *TEXT w178.[1][0] "2"; *TEXT w179.[1][0] "3"; *TEXT w180.[1][0] "4"; *TEXT w181.[1][0] "5"; *TEXT w182.[1][0] "6"; *TEXT w183.[1][0] "7"; *TEXT w184.[1][0] "0"; *TEXT w186.[1][0] "1"; *TEXT w188.[1][0] "2"; *TEXT w190.[1][0] "3"; *TEXT w192.[1][0] "4"; *TEXT w194.[1][0] "5"; *TEXT w196.[1][0] "6"; *TEXT w198.[1][0] "7"; *TEXT w200.[1][0] "0"; *TEXT w201.[1][0] "1"; *TEXT w202.[1][0] "2"; *TEXT w203.[1][0] "3"; *TEXT w204.[1][0] "4"; *TEXT w205.[1][0] "5"; *TEXT w206.[1][0] "6"; *TEXT w207.[1][0] "7"; *TEXT Phi_to_Chans " "; *TEXT PHI_in " "; *TEXT Phi_Delay " "; *TEXT Phase_A " "; *TEXT RESET " "; *TEXT CAP " "; *TEXT Phase_B " "; *TEXT "DelayBuffer"; .ENDS DelayBuffer_S .SUBCKT Enc_Latch_tile_S 1 2 3 4 5 6 7 8 9 15 16 Mtn0 10 8 3 16 TN W=2.00U L=0.80U Mtn4 11 7 10 16 TN W=2.00U L=0.80U Mtp1 4 8 11 15 TP W=3.20U L=0.80U Mtp2 5 11 12 15 TP W=3.20U L=0.80U Mtn1 13 10 2 16 TN W=4.00U L=0.80U Mtp0 12 7 13 15 TP W=3.20U L=0.80U Mtp3 6 12 9 15 TP W=3.20U L=0.80U Mtn3 9 13 1 16 TN W=2.00U L=0.80U *.GND gnd3 1 *.GND gnd4 2 *.GND gnd5 3 *.VDD vdd0 4 *.VDD vdd1 5 *.VDD vdd2 6 *.IN DataStrobe2 7 *.IN D_in 8 *.OUT D_bar 9 *.IN DataStrobe 7 *.Vnwell 15 0 5 *.Vbulk 14 0 0 *.Vpwell 16 0 0 *.Vbulk 14 0 5 *TEXT tn0 " "; *TEXT tn4 " "; *TEXT tp1 " "; *TEXT tp2 " "; *TEXT tn1 " "; *TEXT tp0 " "; *TEXT tp3 " "; *TEXT tn3 " "; *TEXT "Enc_Latch_tile"; .ENDS Enc_Latch_tile_S .SUBCKT EncLatch_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 + 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 128 129 771 772 XEnc_Latch_tile_S_i0 130 131 132 133 134 135 1 65 129 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i1 136 137 138 139 140 141 1 64 128 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i2 142 143 144 145 146 147 1 63 127 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i3 148 149 150 151 152 153 1 62 126 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i4 154 155 156 157 158 159 1 61 125 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i5 160 161 162 163 164 165 1 60 124 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i6 166 167 168 169 170 171 1 59 123 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i7 172 173 174 175 176 177 1 58 122 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i8 178 179 180 181 182 183 1 57 121 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i9 184 185 186 187 188 189 1 56 120 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i10 190 191 192 193 194 195 1 55 119 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i11 196 197 198 199 200 201 1 54 118 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i12 202 203 204 205 206 207 1 53 117 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i13 208 209 210 211 212 213 1 52 116 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i14 214 215 216 217 218 219 1 51 115 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i15 220 221 222 223 224 225 1 50 114 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i16 226 227 228 229 230 231 1 49 113 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i17 232 233 234 235 236 237 1 48 112 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i18 238 239 240 241 242 243 1 47 111 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i19 244 245 246 247 248 249 1 46 110 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i20 250 251 252 253 254 255 1 45 109 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i21 256 257 258 259 260 261 1 44 108 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i22 262 263 264 265 266 267 1 43 107 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i23 268 269 270 271 272 273 1 42 106 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i24 274 275 276 277 278 279 1 41 105 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i25 280 281 282 283 284 285 1 40 104 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i26 286 287 288 289 290 291 1 39 103 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i27 292 293 294 295 296 297 1 38 102 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i28 298 299 300 301 302 303 1 37 101 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i29 304 305 306 307 308 309 1 36 100 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i30 310 311 312 313 314 315 1 35 99 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i31 316 317 318 319 320 321 1 34 98 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i32 322 323 324 325 326 327 1 33 97 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i33 328 329 330 331 332 333 1 32 96 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i34 334 335 336 337 338 339 1 31 95 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i35 340 341 342 343 344 345 1 30 94 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i36 346 347 348 349 350 351 1 29 93 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i37 352 353 354 355 356 357 1 28 92 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i38 358 359 360 361 362 363 1 27 91 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i39 364 365 366 367 368 369 1 26 90 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i40 370 371 372 373 374 375 1 25 89 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i41 376 377 378 379 380 381 1 24 88 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i42 382 383 384 385 386 387 1 23 87 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i43 388 389 390 391 392 393 1 22 86 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i44 394 395 396 397 398 399 1 21 85 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i45 400 401 402 403 404 405 1 20 84 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i46 406 407 408 409 410 411 1 19 83 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i47 412 413 414 415 416 417 1 18 82 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i48 418 419 420 421 422 423 1 17 81 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i49 424 425 426 427 428 429 1 16 80 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i50 430 431 432 433 434 435 1 15 79 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i51 436 437 438 439 440 441 1 14 78 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i52 442 443 444 445 446 447 1 13 77 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i53 448 449 450 451 452 453 1 12 76 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i54 454 455 456 457 458 459 1 11 75 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i55 460 461 462 463 464 465 1 10 74 771 772 + Enc_Latch_tile_S XEnc_Latch_tile_S_i56 466 467 468 469 470 471 1 9 73 771 772 Enc_Latch_tile_S XEnc_Latch_tile_S_i57 472 473 474 475 476 477 1 8 72 771 772 Enc_Latch_tile_S XEnc_Latch_tile_S_i58 478 479 480 481 482 483 1 7 71 771 772 Enc_Latch_tile_S XEnc_Latch_tile_S_i59 484 485 486 487 488 489 1 6 70 771 772 Enc_Latch_tile_S XEnc_Latch_tile_S_i60 490 491 492 493 494 495 1 5 69 771 772 Enc_Latch_tile_S XEnc_Latch_tile_S_i61 496 497 498 499 500 501 1 4 68 771 772 Enc_Latch_tile_S XEnc_Latch_tile_S_i62 502 503 504 505 506 507 1 3 67 771 772 Enc_Latch_tile_S XEnc_Latch_tile_S_i63 508 509 510 511 512 513 1 2 66 771 772 Enc_Latch_tile_S *.IN DataStrobe_0 1 *.IN DataStrobe_63 1 *.IN D_in_[63] 2 *.IN D_in_[62] 3 *.IN D_in_[61] 4 *.IN D_in_[60] 5 *.IN D_in_[59] 6 *.IN D_in_[58] 7 *.IN D_in_[57] 8 *.IN D_in_[56] 9 *.IN D_in_[55] 10 *.IN D_in_[54] 11 *.IN D_in_[53] 12 *.IN D_in_[52] 13 *.IN D_in_[51] 14 *.IN D_in_[50] 15 *.IN D_in_[49] 16 *.IN D_in_[48] 17 *.IN D_in_[47] 18 *.IN D_in_[46] 19 *.IN D_in_[45] 20 *.IN D_in_[44] 21 *.IN D_in_[43] 22 *.IN D_in_[42] 23 *.IN D_in_[41] 24 *.IN D_in_[40] 25 *.IN D_in_[39] 26 *.IN D_in_[38] 27 *.IN D_in_[37] 28 *.IN D_in_[36] 29 *.IN D_in_[35] 30 *.IN D_in_[34] 31 *.IN D_in_[33] 32 *.IN D_in_[32] 33 *.IN D_in_[31] 34 *.IN D_in_[30] 35 *.IN D_in_[29] 36 *.IN D_in_[28] 37 *.IN D_in_[27] 38 *.IN D_in_[26] 39 *.IN D_in_[25] 40 *.IN D_in_[24] 41 *.IN D_in_[23] 42 *.IN D_in_[22] 43 *.IN D_in_[21] 44 *.IN D_in_[20] 45 *.IN D_in_[19] 46 *.IN D_in_[18] 47 *.IN D_in_[17] 48 *.IN D_in_[16] 49 *.IN D_in_[15] 50 *.IN D_in_[14] 51 *.IN D_in_[13] 52 *.IN D_in_[12] 53 *.IN D_in_[11] 54 *.IN D_in_[10] 55 *.IN D_in_[9] 56 *.IN D_in_[8] 57 *.IN D_in_[7] 58 *.IN D_in_[6] 59 *.IN D_in_[5] 60 *.IN D_in_[4] 61 *.IN D_in_[3] 62 *.IN D_in_[2] 63 *.IN D_in_[1] 64 *.IN D_in_[0] 65 *.OUT D_bar_[63] 66 *.OUT D_bar_[62] 67 *.OUT D_bar_[61] 68 *.OUT D_bar_[60] 69 *.OUT D_bar_[59] 70 *.OUT D_bar_[58] 71 *.OUT D_bar_[57] 72 *.OUT D_bar_[56] 73 *.OUT D_bar_[55] 74 *.OUT D_bar_[54] 75 *.OUT D_bar_[53] 76 *.OUT D_bar_[52] 77 *.OUT D_bar_[51] 78 *.OUT D_bar_[50] 79 *.OUT D_bar_[49] 80 *.OUT D_bar_[48] 81 *.OUT D_bar_[47] 82 *.OUT D_bar_[46] 83 *.OUT D_bar_[45] 84 *.OUT D_bar_[44] 85 *.OUT D_bar_[43] 86 *.OUT D_bar_[42] 87 *.OUT D_bar_[41] 88 *.OUT D_bar_[40] 89 *.OUT D_bar_[39] 90 *.OUT D_bar_[38] 91 *.OUT D_bar_[37] 92 *.OUT D_bar_[36] 93 *.OUT D_bar_[35] 94 *.OUT D_bar_[34] 95 *.OUT D_bar_[33] 96 *.OUT D_bar_[32] 97 *.OUT D_bar_[31] 98 *.OUT D_bar_[30] 99 *.OUT D_bar_[29] 100 *.OUT D_bar_[28] 101 *.OUT D_bar_[27] 102 *.OUT D_bar_[26] 103 *.OUT D_bar_[25] 104 *.OUT D_bar_[24] 105 *.OUT D_bar_[23] 106 *.OUT D_bar_[22] 107 *.OUT D_bar_[21] 108 *.OUT D_bar_[20] 109 *.OUT D_bar_[19] 110 *.OUT D_bar_[18] 111 *.OUT D_bar_[17] 112 *.OUT D_bar_[16] 113 *.OUT D_bar_[15] 114 *.OUT D_bar_[14] 115 *.OUT D_bar_[13] 116 *.OUT D_bar_[12] 117 *.OUT D_bar_[11] 118 *.OUT D_bar_[10] 119 *.OUT D_bar_[9] 120 *.OUT D_bar_[8] 121 *.OUT D_bar_[7] 122 *.OUT D_bar_[6] 123 *.OUT D_bar_[5] 124 *.OUT D_bar_[4] 125 *.OUT D_bar_[3] 126 *.OUT D_bar_[2] 127 *.OUT D_bar_[1] 128 *.OUT D_bar_[0] 129 *.GND Enc_Latch_tile_S_i0.gnd3 130 *.GND Enc_Latch_tile_S_i0.gnd4 131 *.GND Enc_Latch_tile_S_i0.gnd5 132 *.VDD Enc_Latch_tile_S_i0.vdd0 133 *.VDD Enc_Latch_tile_S_i0.vdd1 134 *.VDD Enc_Latch_tile_S_i0.vdd2 135 *.IN Enc_Latch_tile_S_i0.DataStrobe2 1 *.IN Enc_Latch_tile_S_i0.D_in 65 *.OUT Enc_Latch_tile_S_i0.D_bar 129 *.IN Enc_Latch_tile_S_i0.DataStrobe 1 *.GND Enc_Latch_tile_S_i1.gnd3 136 *.GND Enc_Latch_tile_S_i1.gnd4 137 *.GND Enc_Latch_tile_S_i1.gnd5 138 *.VDD Enc_Latch_tile_S_i1.vdd0 139 *.VDD Enc_Latch_tile_S_i1.vdd1 140 *.VDD Enc_Latch_tile_S_i1.vdd2 141 *.IN Enc_Latch_tile_S_i1.DataStrobe2 1 *.IN Enc_Latch_tile_S_i1.D_in 64 *.OUT Enc_Latch_tile_S_i1.D_bar 128 *.IN Enc_Latch_tile_S_i1.DataStrobe 1 *.GND Enc_Latch_tile_S_i2.gnd3 142 *.GND Enc_Latch_tile_S_i2.gnd4 143 *.GND Enc_Latch_tile_S_i2.gnd5 144 *.VDD Enc_Latch_tile_S_i2.vdd0 145 *.VDD Enc_Latch_tile_S_i2.vdd1 146 *.VDD Enc_Latch_tile_S_i2.vdd2 147 *.IN Enc_Latch_tile_S_i2.DataStrobe2 1 *.IN Enc_Latch_tile_S_i2.D_in 63 *.OUT Enc_Latch_tile_S_i2.D_bar 127 *.IN Enc_Latch_tile_S_i2.DataStrobe 1 *.GND Enc_Latch_tile_S_i3.gnd3 148 *.GND Enc_Latch_tile_S_i3.gnd4 149 *.GND Enc_Latch_tile_S_i3.gnd5 150 *.VDD Enc_Latch_tile_S_i3.vdd0 151 *.VDD Enc_Latch_tile_S_i3.vdd1 152 *.VDD Enc_Latch_tile_S_i3.vdd2 153 *.IN Enc_Latch_tile_S_i3.DataStrobe2 1 *.IN Enc_Latch_tile_S_i3.D_in 62 *.OUT Enc_Latch_tile_S_i3.D_bar 126 *.IN Enc_Latch_tile_S_i3.DataStrobe 1 *.GND Enc_Latch_tile_S_i4.gnd3 154 *.GND Enc_Latch_tile_S_i4.gnd4 155 *.GND Enc_Latch_tile_S_i4.gnd5 156 *.VDD Enc_Latch_tile_S_i4.vdd0 157 *.VDD Enc_Latch_tile_S_i4.vdd1 158 *.VDD Enc_Latch_tile_S_i4.vdd2 159 *.IN Enc_Latch_tile_S_i4.DataStrobe2 1 *.IN Enc_Latch_tile_S_i4.D_in 61 *.OUT Enc_Latch_tile_S_i4.D_bar 125 *.IN Enc_Latch_tile_S_i4.DataStrobe 1 *.GND Enc_Latch_tile_S_i5.gnd3 160 *.GND Enc_Latch_tile_S_i5.gnd4 161 *.GND Enc_Latch_tile_S_i5.gnd5 162 *.VDD Enc_Latch_tile_S_i5.vdd0 163 *.VDD Enc_Latch_tile_S_i5.vdd1 164 *.VDD Enc_Latch_tile_S_i5.vdd2 165 *.IN Enc_Latch_tile_S_i5.DataStrobe2 1 *.IN Enc_Latch_tile_S_i5.D_in 60 *.OUT Enc_Latch_tile_S_i5.D_bar 124 *.IN Enc_Latch_tile_S_i5.DataStrobe 1 *.GND Enc_Latch_tile_S_i6.gnd3 166 *.GND Enc_Latch_tile_S_i6.gnd4 167 *.GND Enc_Latch_tile_S_i6.gnd5 168 *.VDD Enc_Latch_tile_S_i6.vdd0 169 *.VDD Enc_Latch_tile_S_i6.vdd1 170 *.VDD Enc_Latch_tile_S_i6.vdd2 171 *.IN Enc_Latch_tile_S_i6.DataStrobe2 1 *.IN Enc_Latch_tile_S_i6.D_in 59 *.OUT Enc_Latch_tile_S_i6.D_bar 123 *.IN Enc_Latch_tile_S_i6.DataStrobe 1 *.GND Enc_Latch_tile_S_i7.gnd3 172 *.GND Enc_Latch_tile_S_i7.gnd4 173 *.GND Enc_Latch_tile_S_i7.gnd5 174 *.VDD Enc_Latch_tile_S_i7.vdd0 175 *.VDD Enc_Latch_tile_S_i7.vdd1 176 *.VDD Enc_Latch_tile_S_i7.vdd2 177 *.IN Enc_Latch_tile_S_i7.DataStrobe2 1 *.IN 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w94.[1][0] "46"; *TEXT w95.[1][14] "47"; *TEXT w96.[1][0] "47"; *TEXT w97.[1][14] "48"; *TEXT w98.[1][0] "48"; *TEXT w99.[1][14] "49"; *TEXT w100.[1][0] "49"; *TEXT w101.[1][14] "50"; *TEXT w102.[1][0] "50"; *TEXT w103.[1][14] "51"; *TEXT w104.[1][0] "51"; *TEXT w105.[1][14] "52"; *TEXT w106.[1][0] "52"; *TEXT w107.[1][14] "53"; *TEXT w108.[1][0] "53"; *TEXT w109.[1][14] "54"; *TEXT w110.[1][0] "54"; *TEXT w111.[1][14] "55"; *TEXT w112.[1][0] "55"; *TEXT w113.[1][14] "56"; *TEXT w114.[1][0] "56"; *TEXT w115.[1][14] "57"; *TEXT w116.[1][0] "57"; *TEXT w117.[1][14] "58"; *TEXT w118.[1][0] "58"; *TEXT w119.[1][14] "59"; *TEXT w120.[1][0] "59"; *TEXT w121.[1][14] "60"; *TEXT w122.[1][0] "60"; *TEXT w123.[1][14] "61"; *TEXT w124.[1][0] "61"; *TEXT w125.[1][14] "62"; *TEXT w126.[1][0] "62"; *TEXT w127.[1][14] "63"; *TEXT w128.[1][0] "63"; .ENDS EncLatch_S .SUBCKT Encode1_tile_S 1 2 3 4 5 6 7 8 12 13 Mtn0 10 9 1 13 TN W=2.00U L=0.80U Mtn1 8 6 10 13 TN W=2.00U L=0.80U Mtp0 2 7 8 12 TP W=1.60U L=1.20U Mtn2 9 5 3 13 TN W=2.00U L=0.80U Mtp3 4 5 9 12 TP W=2.80U L=0.80U *.GND gnd0 1 *.VDD vdd0 2 *.GND gnd1 3 *.VDD vdd1 4 *.IN DFF_to_Enc1inv 5 *.IN DFF_to_Enc1 6 *.GND gnd2 7 *.OUT Enc1_to_Enc2 8 *.Vnwell 12 0 5 *.Vbulk 11 0 0 *.Vpwell 13 0 0 *.Vbulk 11 0 5 *TEXT tn0 " "; *TEXT tn1 " "; *TEXT tp0 " "; *TEXT tn2 " "; *TEXT tp3 " "; *TEXT "Encode1_tile"; .ENDS Encode1_tile_S .SUBCKT Encode1_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 + 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 570 571 XEncode1_tile_S_i0 128 129 130 131 62 63 132 127 570 571 Encode1_tile_S XEncode1_tile_S_i1 133 134 135 136 61 62 137 126 570 571 Encode1_tile_S XEncode1_tile_S_i2 138 139 140 141 60 61 142 125 570 571 Encode1_tile_S XEncode1_tile_S_i3 143 144 145 146 59 60 147 124 570 571 Encode1_tile_S XEncode1_tile_S_i4 148 149 150 151 58 59 152 123 570 571 Encode1_tile_S XEncode1_tile_S_i5 153 154 155 156 57 58 157 122 570 571 Encode1_tile_S XEncode1_tile_S_i6 158 159 160 161 56 57 162 121 570 571 Encode1_tile_S XEncode1_tile_S_i7 163 164 165 166 55 56 167 120 570 571 Encode1_tile_S XEncode1_tile_S_i8 168 169 170 171 54 55 172 119 570 571 Encode1_tile_S XEncode1_tile_S_i9 173 174 175 176 53 54 177 118 570 571 Encode1_tile_S XEncode1_tile_S_i10 178 179 180 181 52 53 182 117 570 571 Encode1_tile_S XEncode1_tile_S_i11 183 184 185 186 51 52 187 116 570 571 Encode1_tile_S XEncode1_tile_S_i12 188 189 190 191 50 51 192 115 570 571 Encode1_tile_S XEncode1_tile_S_i13 193 194 195 196 49 50 197 114 570 571 Encode1_tile_S XEncode1_tile_S_i14 198 199 200 201 48 49 202 113 570 571 Encode1_tile_S XEncode1_tile_S_i15 203 204 205 206 47 48 207 112 570 571 Encode1_tile_S XEncode1_tile_S_i16 208 209 210 211 46 47 212 111 570 571 Encode1_tile_S XEncode1_tile_S_i17 213 214 215 216 45 46 217 110 570 571 Encode1_tile_S XEncode1_tile_S_i18 218 219 220 221 44 45 222 109 570 571 Encode1_tile_S XEncode1_tile_S_i19 223 224 225 226 43 44 227 108 570 571 Encode1_tile_S XEncode1_tile_S_i20 228 229 230 231 42 43 232 107 570 571 Encode1_tile_S XEncode1_tile_S_i21 233 234 235 236 41 42 237 106 570 571 Encode1_tile_S XEncode1_tile_S_i22 238 239 240 241 40 41 242 105 570 571 Encode1_tile_S XEncode1_tile_S_i23 243 244 245 246 39 40 247 104 570 571 Encode1_tile_S XEncode1_tile_S_i24 248 249 250 251 38 39 252 103 570 571 Encode1_tile_S XEncode1_tile_S_i25 253 254 255 256 37 38 257 102 570 571 Encode1_tile_S XEncode1_tile_S_i26 258 259 260 261 36 37 262 101 570 571 Encode1_tile_S XEncode1_tile_S_i27 263 264 265 266 35 36 267 100 570 571 Encode1_tile_S XEncode1_tile_S_i28 268 269 270 271 34 35 272 99 570 571 Encode1_tile_S XEncode1_tile_S_i29 273 274 275 276 33 34 277 98 570 571 Encode1_tile_S XEncode1_tile_S_i30 278 279 280 281 32 33 282 97 570 571 Encode1_tile_S XEncode1_tile_S_i31 283 284 285 286 31 32 287 96 570 571 Encode1_tile_S XEncode1_tile_S_i32 288 289 290 291 30 31 292 95 570 571 Encode1_tile_S XEncode1_tile_S_i33 293 294 295 296 29 30 297 94 570 571 Encode1_tile_S XEncode1_tile_S_i34 298 299 300 301 28 29 302 93 570 571 Encode1_tile_S XEncode1_tile_S_i35 303 304 305 306 27 28 307 92 570 571 Encode1_tile_S XEncode1_tile_S_i36 308 309 310 311 26 27 312 91 570 571 Encode1_tile_S XEncode1_tile_S_i37 313 314 315 316 25 26 317 90 570 571 Encode1_tile_S XEncode1_tile_S_i38 318 319 320 321 24 25 322 89 570 571 Encode1_tile_S XEncode1_tile_S_i39 323 324 325 326 23 24 327 88 570 571 Encode1_tile_S XEncode1_tile_S_i40 328 329 330 331 22 23 332 87 570 571 Encode1_tile_S XEncode1_tile_S_i41 333 334 335 336 21 22 337 86 570 571 Encode1_tile_S XEncode1_tile_S_i42 338 339 340 341 20 21 342 85 570 571 Encode1_tile_S XEncode1_tile_S_i43 343 344 345 346 19 20 347 84 570 571 Encode1_tile_S XEncode1_tile_S_i44 348 349 350 351 18 19 352 83 570 571 Encode1_tile_S XEncode1_tile_S_i45 353 354 355 356 17 18 357 82 570 571 Encode1_tile_S XEncode1_tile_S_i46 358 359 360 361 16 17 362 81 570 571 Encode1_tile_S XEncode1_tile_S_i47 363 364 365 366 15 16 367 80 570 571 Encode1_tile_S XEncode1_tile_S_i48 368 369 370 371 14 15 372 79 570 571 Encode1_tile_S XEncode1_tile_S_i49 373 374 375 376 13 14 377 78 570 571 Encode1_tile_S XEncode1_tile_S_i50 378 379 380 381 12 13 382 77 570 571 Encode1_tile_S XEncode1_tile_S_i51 383 384 385 386 11 12 387 76 570 571 Encode1_tile_S XEncode1_tile_S_i52 388 389 390 391 10 11 392 75 570 571 Encode1_tile_S XEncode1_tile_S_i53 393 394 395 396 9 10 397 74 570 571 Encode1_tile_S XEncode1_tile_S_i54 398 399 400 401 8 9 402 73 570 571 Encode1_tile_S XEncode1_tile_S_i55 403 404 405 406 7 8 407 72 570 571 Encode1_tile_S XEncode1_tile_S_i56 408 409 410 411 6 7 412 71 570 571 Encode1_tile_S XEncode1_tile_S_i57 413 414 415 416 5 6 417 70 570 571 Encode1_tile_S XEncode1_tile_S_i58 418 419 420 421 4 5 422 69 570 571 Encode1_tile_S XEncode1_tile_S_i59 423 424 425 426 3 4 427 68 570 571 Encode1_tile_S XEncode1_tile_S_i60 428 429 430 431 2 3 432 67 570 571 Encode1_tile_S XEncode1_tile_S_i61 433 434 435 436 1 2 437 66 570 571 Encode1_tile_S XEncode1_tile_S_i62 438 439 440 441 64 1 442 65 570 571 Encode1_tile_S *.IN DFF_to_Enc1_[62] 1 *.IN DFF_to_Enc1_[61] 2 *.IN DFF_to_Enc1_[60] 3 *.IN DFF_to_Enc1_[59] 4 *.IN DFF_to_Enc1_[58] 5 *.IN DFF_to_Enc1_[57] 6 *.IN DFF_to_Enc1_[56] 7 *.IN DFF_to_Enc1_[55] 8 *.IN DFF_to_Enc1_[54] 9 *.IN DFF_to_Enc1_[53] 10 *.IN DFF_to_Enc1_[52] 11 *.IN DFF_to_Enc1_[51] 12 *.IN DFF_to_Enc1_[50] 13 *.IN DFF_to_Enc1_[49] 14 *.IN DFF_to_Enc1_[48] 15 *.IN DFF_to_Enc1_[47] 16 *.IN DFF_to_Enc1_[46] 17 *.IN DFF_to_Enc1_[45] 18 *.IN DFF_to_Enc1_[44] 19 *.IN DFF_to_Enc1_[43] 20 *.IN DFF_to_Enc1_[42] 21 *.IN DFF_to_Enc1_[41] 22 *.IN DFF_to_Enc1_[40] 23 *.IN DFF_to_Enc1_[39] 24 *.IN DFF_to_Enc1_[38] 25 *.IN DFF_to_Enc1_[37] 26 *.IN DFF_to_Enc1_[36] 27 *.IN DFF_to_Enc1_[35] 28 *.IN DFF_to_Enc1_[34] 29 *.IN DFF_to_Enc1_[33] 30 *.IN DFF_to_Enc1_[32] 31 *.IN DFF_to_Enc1_[31] 32 *.IN DFF_to_Enc1_[30] 33 *.IN DFF_to_Enc1_[29] 34 *.IN DFF_to_Enc1_[28] 35 *.IN DFF_to_Enc1_[27] 36 *.IN DFF_to_Enc1_[26] 37 *.IN DFF_to_Enc1_[25] 38 *.IN DFF_to_Enc1_[24] 39 *.IN DFF_to_Enc1_[23] 40 *.IN DFF_to_Enc1_[22] 41 *.IN DFF_to_Enc1_[21] 42 *.IN DFF_to_Enc1_[20] 43 *.IN DFF_to_Enc1_[19] 44 *.IN DFF_to_Enc1_[18] 45 *.IN DFF_to_Enc1_[17] 46 *.IN DFF_to_Enc1_[16] 47 *.IN DFF_to_Enc1_[15] 48 *.IN DFF_to_Enc1_[14] 49 *.IN DFF_to_Enc1_[13] 50 *.IN DFF_to_Enc1_[12] 51 *.IN DFF_to_Enc1_[11] 52 *.IN DFF_to_Enc1_[10] 53 *.IN DFF_to_Enc1_[9] 54 *.IN DFF_to_Enc1_[8] 55 *.IN DFF_to_Enc1_[7] 56 *.IN DFF_to_Enc1_[6] 57 *.IN DFF_to_Enc1_[5] 58 *.IN DFF_to_Enc1_[4] 59 *.IN DFF_to_Enc1_[3] 60 *.IN DFF_to_Enc1_[2] 61 *.IN DFF_to_Enc1_[1] 62 *.IN DFF_to_Enc1_[0] 63 *.IN Dff_to_Enc1inv_[62] 64 *.IN Dff_to_Enc1inv_[61] 1 *.IN Dff_to_Enc1inv_[60] 2 *.IN Dff_to_Enc1inv_[59] 3 *.IN Dff_to_Enc1inv_[58] 4 *.IN Dff_to_Enc1inv_[57] 5 *.IN Dff_to_Enc1inv_[56] 6 *.IN Dff_to_Enc1inv_[55] 7 *.IN Dff_to_Enc1inv_[54] 8 *.IN Dff_to_Enc1inv_[53] 9 *.IN Dff_to_Enc1inv_[52] 10 *.IN Dff_to_Enc1inv_[51] 11 *.IN Dff_to_Enc1inv_[50] 12 *.IN Dff_to_Enc1inv_[49] 13 *.IN Dff_to_Enc1inv_[48] 14 *.IN Dff_to_Enc1inv_[47] 15 *.IN Dff_to_Enc1inv_[46] 16 *.IN Dff_to_Enc1inv_[45] 17 *.IN Dff_to_Enc1inv_[44] 18 *.IN Dff_to_Enc1inv_[43] 19 *.IN Dff_to_Enc1inv_[42] 20 *.IN Dff_to_Enc1inv_[41] 21 *.IN Dff_to_Enc1inv_[40] 22 *.IN Dff_to_Enc1inv_[39] 23 *.IN Dff_to_Enc1inv_[38] 24 *.IN Dff_to_Enc1inv_[37] 25 *.IN Dff_to_Enc1inv_[36] 26 *.IN Dff_to_Enc1inv_[35] 27 *.IN Dff_to_Enc1inv_[34] 28 *.IN Dff_to_Enc1inv_[33] 29 *.IN Dff_to_Enc1inv_[32] 30 *.IN Dff_to_Enc1inv_[31] 31 *.IN Dff_to_Enc1inv_[30] 32 *.IN Dff_to_Enc1inv_[29] 33 *.IN Dff_to_Enc1inv_[28] 34 *.IN Dff_to_Enc1inv_[27] 35 *.IN Dff_to_Enc1inv_[26] 36 *.IN Dff_to_Enc1inv_[25] 37 *.IN Dff_to_Enc1inv_[24] 38 *.IN Dff_to_Enc1inv_[23] 39 *.IN Dff_to_Enc1inv_[22] 40 *.IN Dff_to_Enc1inv_[21] 41 *.IN Dff_to_Enc1inv_[20] 42 *.IN Dff_to_Enc1inv_[19] 43 *.IN Dff_to_Enc1inv_[18] 44 *.IN Dff_to_Enc1inv_[17] 45 *.IN Dff_to_Enc1inv_[16] 46 *.IN Dff_to_Enc1inv_[15] 47 *.IN Dff_to_Enc1inv_[14] 48 *.IN Dff_to_Enc1inv_[13] 49 *.IN Dff_to_Enc1inv_[12] 50 *.IN Dff_to_Enc1inv_[11] 51 *.IN Dff_to_Enc1inv_[10] 52 *.IN Dff_to_Enc1inv_[9] 53 *.IN Dff_to_Enc1inv_[8] 54 *.IN Dff_to_Enc1inv_[7] 55 *.IN Dff_to_Enc1inv_[6] 56 *.IN Dff_to_Enc1inv_[5] 57 *.IN Dff_to_Enc1inv_[4] 58 *.IN Dff_to_Enc1inv_[3] 59 *.IN Dff_to_Enc1inv_[2] 60 *.IN Dff_to_Enc1inv_[1] 61 *.IN Dff_to_Enc1inv_[0] 62 *.OUT Enc1_to_Enc2_[62] 65 *.OUT Enc1_to_Enc2_[61] 66 *.OUT Enc1_to_Enc2_[60] 67 *.OUT Enc1_to_Enc2_[59] 68 *.OUT Enc1_to_Enc2_[58] 69 *.OUT Enc1_to_Enc2_[57] 70 *.OUT Enc1_to_Enc2_[56] 71 *.OUT Enc1_to_Enc2_[55] 72 *.OUT Enc1_to_Enc2_[54] 73 *.OUT Enc1_to_Enc2_[53] 74 *.OUT Enc1_to_Enc2_[52] 75 *.OUT Enc1_to_Enc2_[51] 76 *.OUT Enc1_to_Enc2_[50] 77 *.OUT Enc1_to_Enc2_[49] 78 *.OUT Enc1_to_Enc2_[48] 79 *.OUT Enc1_to_Enc2_[47] 80 *.OUT Enc1_to_Enc2_[46] 81 *.OUT Enc1_to_Enc2_[45] 82 *.OUT Enc1_to_Enc2_[44] 83 *.OUT Enc1_to_Enc2_[43] 84 *.OUT Enc1_to_Enc2_[42] 85 *.OUT Enc1_to_Enc2_[41] 86 *.OUT Enc1_to_Enc2_[40] 87 *.OUT Enc1_to_Enc2_[39] 88 *.OUT Enc1_to_Enc2_[38] 89 *.OUT Enc1_to_Enc2_[37] 90 *.OUT Enc1_to_Enc2_[36] 91 *.OUT Enc1_to_Enc2_[35] 92 *.OUT Enc1_to_Enc2_[34] 93 *.OUT Enc1_to_Enc2_[33] 94 *.OUT Enc1_to_Enc2_[32] 95 *.OUT Enc1_to_Enc2_[31] 96 *.OUT Enc1_to_Enc2_[30] 97 *.OUT Enc1_to_Enc2_[29] 98 *.OUT Enc1_to_Enc2_[28] 99 *.OUT Enc1_to_Enc2_[27] 100 *.OUT Enc1_to_Enc2_[26] 101 *.OUT Enc1_to_Enc2_[25] 102 *.OUT Enc1_to_Enc2_[24] 103 *.OUT Enc1_to_Enc2_[23] 104 *.OUT Enc1_to_Enc2_[22] 105 *.OUT Enc1_to_Enc2_[21] 106 *.OUT Enc1_to_Enc2_[20] 107 *.OUT Enc1_to_Enc2_[19] 108 *.OUT Enc1_to_Enc2_[18] 109 *.OUT Enc1_to_Enc2_[17] 110 *.OUT Enc1_to_Enc2_[16] 111 *.OUT Enc1_to_Enc2_[15] 112 *.OUT Enc1_to_Enc2_[14] 113 *.OUT Enc1_to_Enc2_[13] 114 *.OUT Enc1_to_Enc2_[12] 115 *.OUT Enc1_to_Enc2_[11] 116 *.OUT Enc1_to_Enc2_[10] 117 *.OUT Enc1_to_Enc2_[9] 118 *.OUT Enc1_to_Enc2_[8] 119 *.OUT Enc1_to_Enc2_[7] 120 *.OUT Enc1_to_Enc2_[6] 121 *.OUT Enc1_to_Enc2_[5] 122 *.OUT Enc1_to_Enc2_[4] 123 *.OUT Enc1_to_Enc2_[3] 124 *.OUT Enc1_to_Enc2_[2] 125 *.OUT Enc1_to_Enc2_[1] 126 *.OUT Enc1_to_Enc2_[0] 127 *.GND Encode1_tile_S_i0.gnd0 128 *.VDD Encode1_tile_S_i0.vdd0 129 *.GND Encode1_tile_S_i0.gnd1 130 *.VDD Encode1_tile_S_i0.vdd1 131 *.IN Encode1_tile_S_i0.DFF_to_Enc1inv 62 *.IN Encode1_tile_S_i0.DFF_to_Enc1 63 *.GND Encode1_tile_S_i0.gnd2 132 *.OUT Encode1_tile_S_i0.Enc1_to_Enc2 127 *.GND Encode1_tile_S_i1.gnd0 133 *.VDD Encode1_tile_S_i1.vdd0 134 *.GND Encode1_tile_S_i1.gnd1 135 *.VDD Encode1_tile_S_i1.vdd1 136 *.IN Encode1_tile_S_i1.DFF_to_Enc1inv 61 *.IN Encode1_tile_S_i1.DFF_to_Enc1 62 *.GND Encode1_tile_S_i1.gnd2 137 *.OUT Encode1_tile_S_i1.Enc1_to_Enc2 126 *.GND Encode1_tile_S_i2.gnd0 138 *.VDD Encode1_tile_S_i2.vdd0 139 *.GND Encode1_tile_S_i2.gnd1 140 *.VDD Encode1_tile_S_i2.vdd1 141 *.IN Encode1_tile_S_i2.DFF_to_Enc1inv 60 *.IN Encode1_tile_S_i2.DFF_to_Enc1 61 *.GND Encode1_tile_S_i2.gnd2 142 *.OUT Encode1_tile_S_i2.Enc1_to_Enc2 125 *.GND Encode1_tile_S_i3.gnd0 143 *.VDD Encode1_tile_S_i3.vdd0 144 *.GND Encode1_tile_S_i3.gnd1 145 *.VDD Encode1_tile_S_i3.vdd1 146 *.IN Encode1_tile_S_i3.DFF_to_Enc1inv 59 *.IN Encode1_tile_S_i3.DFF_to_Enc1 60 *.GND Encode1_tile_S_i3.gnd2 147 *.OUT Encode1_tile_S_i3.Enc1_to_Enc2 124 *.GND Encode1_tile_S_i4.gnd0 148 *.VDD Encode1_tile_S_i4.vdd0 149 *.GND Encode1_tile_S_i4.gnd1 150 *.VDD Encode1_tile_S_i4.vdd1 151 *.IN Encode1_tile_S_i4.DFF_to_Enc1inv 58 *.IN Encode1_tile_S_i4.DFF_to_Enc1 59 *.GND Encode1_tile_S_i4.gnd2 152 *.OUT Encode1_tile_S_i4.Enc1_to_Enc2 123 *.GND Encode1_tile_S_i5.gnd0 153 *.VDD Encode1_tile_S_i5.vdd0 154 *.GND Encode1_tile_S_i5.gnd1 155 *.VDD Encode1_tile_S_i5.vdd1 156 *.IN Encode1_tile_S_i5.DFF_to_Enc1inv 57 *.IN Encode1_tile_S_i5.DFF_to_Enc1 58 *.GND Encode1_tile_S_i5.gnd2 157 *.OUT Encode1_tile_S_i5.Enc1_to_Enc2 122 *.GND Encode1_tile_S_i6.gnd0 158 *.VDD Encode1_tile_S_i6.vdd0 159 *.GND Encode1_tile_S_i6.gnd1 160 *.VDD Encode1_tile_S_i6.vdd1 161 *.IN Encode1_tile_S_i6.DFF_to_Enc1inv 56 *.IN Encode1_tile_S_i6.DFF_to_Enc1 57 *.GND Encode1_tile_S_i6.gnd2 162 *.OUT Encode1_tile_S_i6.Enc1_to_Enc2 121 *.GND Encode1_tile_S_i7.gnd0 163 *.VDD Encode1_tile_S_i7.vdd0 164 *.GND Encode1_tile_S_i7.gnd1 165 *.VDD Encode1_tile_S_i7.vdd1 166 *.IN Encode1_tile_S_i7.DFF_to_Enc1inv 55 *.IN Encode1_tile_S_i7.DFF_to_Enc1 56 *.GND Encode1_tile_S_i7.gnd2 167 *.OUT Encode1_tile_S_i7.Enc1_to_Enc2 120 *.GND Encode1_tile_S_i8.gnd0 168 *.VDD Encode1_tile_S_i8.vdd0 169 *.GND Encode1_tile_S_i8.gnd1 170 *.VDD Encode1_tile_S_i8.vdd1 171 *.IN Encode1_tile_S_i8.DFF_to_Enc1inv 54 *.IN Encode1_tile_S_i8.DFF_to_Enc1 55 *.GND Encode1_tile_S_i8.gnd2 172 *.OUT Encode1_tile_S_i8.Enc1_to_Enc2 119 *.GND Encode1_tile_S_i9.gnd0 173 *.VDD Encode1_tile_S_i9.vdd0 174 *.GND Encode1_tile_S_i9.gnd1 175 *.VDD Encode1_tile_S_i9.vdd1 176 *.IN Encode1_tile_S_i9.DFF_to_Enc1inv 53 *.IN Encode1_tile_S_i9.DFF_to_Enc1 54 *.GND Encode1_tile_S_i9.gnd2 177 *.OUT Encode1_tile_S_i9.Enc1_to_Enc2 118 *.GND Encode1_tile_S_i10.gnd0 178 *.VDD Encode1_tile_S_i10.vdd0 179 *.GND Encode1_tile_S_i10.gnd1 180 *.VDD Encode1_tile_S_i10.vdd1 181 *.IN Encode1_tile_S_i10.DFF_to_Enc1inv 52 *.IN Encode1_tile_S_i10.DFF_to_Enc1 53 *.GND Encode1_tile_S_i10.gnd2 182 *.OUT Encode1_tile_S_i10.Enc1_to_Enc2 117 *.GND Encode1_tile_S_i11.gnd0 183 *.VDD Encode1_tile_S_i11.vdd0 184 *.GND Encode1_tile_S_i11.gnd1 185 *.VDD Encode1_tile_S_i11.vdd1 186 *.IN Encode1_tile_S_i11.DFF_to_Enc1inv 51 *.IN Encode1_tile_S_i11.DFF_to_Enc1 52 *.GND Encode1_tile_S_i11.gnd2 187 *.OUT Encode1_tile_S_i11.Enc1_to_Enc2 116 *.GND Encode1_tile_S_i12.gnd0 188 *.VDD Encode1_tile_S_i12.vdd0 189 *.GND Encode1_tile_S_i12.gnd1 190 *.VDD Encode1_tile_S_i12.vdd1 191 *.IN Encode1_tile_S_i12.DFF_to_Enc1inv 50 *.IN Encode1_tile_S_i12.DFF_to_Enc1 51 *.GND Encode1_tile_S_i12.gnd2 192 *.OUT Encode1_tile_S_i12.Enc1_to_Enc2 115 *.GND Encode1_tile_S_i13.gnd0 193 *.VDD Encode1_tile_S_i13.vdd0 194 *.GND Encode1_tile_S_i13.gnd1 195 *.VDD Encode1_tile_S_i13.vdd1 196 *.IN Encode1_tile_S_i13.DFF_to_Enc1inv 49 *.IN Encode1_tile_S_i13.DFF_to_Enc1 50 *.GND Encode1_tile_S_i13.gnd2 197 *.OUT Encode1_tile_S_i13.Enc1_to_Enc2 114 *.GND Encode1_tile_S_i14.gnd0 198 *.VDD Encode1_tile_S_i14.vdd0 199 *.GND Encode1_tile_S_i14.gnd1 200 *.VDD Encode1_tile_S_i14.vdd1 201 *.IN Encode1_tile_S_i14.DFF_to_Enc1inv 48 *.IN Encode1_tile_S_i14.DFF_to_Enc1 49 *.GND Encode1_tile_S_i14.gnd2 202 *.OUT Encode1_tile_S_i14.Enc1_to_Enc2 113 *.GND Encode1_tile_S_i15.gnd0 203 *.VDD Encode1_tile_S_i15.vdd0 204 *.GND Encode1_tile_S_i15.gnd1 205 *.VDD Encode1_tile_S_i15.vdd1 206 *.IN Encode1_tile_S_i15.DFF_to_Enc1inv 47 *.IN Encode1_tile_S_i15.DFF_to_Enc1 48 *.GND Encode1_tile_S_i15.gnd2 207 *.OUT Encode1_tile_S_i15.Enc1_to_Enc2 112 *.GND Encode1_tile_S_i16.gnd0 208 *.VDD Encode1_tile_S_i16.vdd0 209 *.GND Encode1_tile_S_i16.gnd1 210 *.VDD Encode1_tile_S_i16.vdd1 211 *.IN Encode1_tile_S_i16.DFF_to_Enc1inv 46 *.IN Encode1_tile_S_i16.DFF_to_Enc1 47 *.GND Encode1_tile_S_i16.gnd2 212 *.OUT Encode1_tile_S_i16.Enc1_to_Enc2 111 *.GND Encode1_tile_S_i17.gnd0 213 *.VDD Encode1_tile_S_i17.vdd0 214 *.GND Encode1_tile_S_i17.gnd1 215 *.VDD Encode1_tile_S_i17.vdd1 216 *.IN Encode1_tile_S_i17.DFF_to_Enc1inv 45 *.IN Encode1_tile_S_i17.DFF_to_Enc1 46 *.GND Encode1_tile_S_i17.gnd2 217 *.OUT Encode1_tile_S_i17.Enc1_to_Enc2 110 *.GND Encode1_tile_S_i18.gnd0 218 *.VDD Encode1_tile_S_i18.vdd0 219 *.GND Encode1_tile_S_i18.gnd1 220 *.VDD Encode1_tile_S_i18.vdd1 221 *.IN Encode1_tile_S_i18.DFF_to_Enc1inv 44 *.IN Encode1_tile_S_i18.DFF_to_Enc1 45 *.GND Encode1_tile_S_i18.gnd2 222 *.OUT Encode1_tile_S_i18.Enc1_to_Enc2 109 *.GND Encode1_tile_S_i19.gnd0 223 *.VDD Encode1_tile_S_i19.vdd0 224 *.GND Encode1_tile_S_i19.gnd1 225 *.VDD Encode1_tile_S_i19.vdd1 226 *.IN Encode1_tile_S_i19.DFF_to_Enc1inv 43 *.IN Encode1_tile_S_i19.DFF_to_Enc1 44 *.GND Encode1_tile_S_i19.gnd2 227 *.OUT Encode1_tile_S_i19.Enc1_to_Enc2 108 *.GND Encode1_tile_S_i20.gnd0 228 *.VDD Encode1_tile_S_i20.vdd0 229 *.GND Encode1_tile_S_i20.gnd1 230 *.VDD Encode1_tile_S_i20.vdd1 231 *.IN Encode1_tile_S_i20.DFF_to_Enc1inv 42 *.IN Encode1_tile_S_i20.DFF_to_Enc1 43 *.GND Encode1_tile_S_i20.gnd2 232 *.OUT Encode1_tile_S_i20.Enc1_to_Enc2 107 *.GND Encode1_tile_S_i21.gnd0 233 *.VDD Encode1_tile_S_i21.vdd0 234 *.GND Encode1_tile_S_i21.gnd1 235 *.VDD Encode1_tile_S_i21.vdd1 236 *.IN Encode1_tile_S_i21.DFF_to_Enc1inv 41 *.IN Encode1_tile_S_i21.DFF_to_Enc1 42 *.GND Encode1_tile_S_i21.gnd2 237 *.OUT Encode1_tile_S_i21.Enc1_to_Enc2 106 *.GND Encode1_tile_S_i22.gnd0 238 *.VDD Encode1_tile_S_i22.vdd0 239 *.GND Encode1_tile_S_i22.gnd1 240 *.VDD Encode1_tile_S_i22.vdd1 241 *.IN Encode1_tile_S_i22.DFF_to_Enc1inv 40 *.IN Encode1_tile_S_i22.DFF_to_Enc1 41 *.GND Encode1_tile_S_i22.gnd2 242 *.OUT Encode1_tile_S_i22.Enc1_to_Enc2 105 *.GND Encode1_tile_S_i23.gnd0 243 *.VDD Encode1_tile_S_i23.vdd0 244 *.GND Encode1_tile_S_i23.gnd1 245 *.VDD Encode1_tile_S_i23.vdd1 246 *.IN Encode1_tile_S_i23.DFF_to_Enc1inv 39 *.IN Encode1_tile_S_i23.DFF_to_Enc1 40 *.GND Encode1_tile_S_i23.gnd2 247 *.OUT Encode1_tile_S_i23.Enc1_to_Enc2 104 *.GND Encode1_tile_S_i24.gnd0 248 *.VDD Encode1_tile_S_i24.vdd0 249 *.GND Encode1_tile_S_i24.gnd1 250 *.VDD Encode1_tile_S_i24.vdd1 251 *.IN Encode1_tile_S_i24.DFF_to_Enc1inv 38 *.IN Encode1_tile_S_i24.DFF_to_Enc1 39 *.GND Encode1_tile_S_i24.gnd2 252 *.OUT Encode1_tile_S_i24.Enc1_to_Enc2 103 *.GND Encode1_tile_S_i25.gnd0 253 *.VDD Encode1_tile_S_i25.vdd0 254 *.GND Encode1_tile_S_i25.gnd1 255 *.VDD Encode1_tile_S_i25.vdd1 256 *.IN Encode1_tile_S_i25.DFF_to_Enc1inv 37 *.IN Encode1_tile_S_i25.DFF_to_Enc1 38 *.GND Encode1_tile_S_i25.gnd2 257 *.OUT Encode1_tile_S_i25.Enc1_to_Enc2 102 *.GND Encode1_tile_S_i26.gnd0 258 *.VDD Encode1_tile_S_i26.vdd0 259 *.GND Encode1_tile_S_i26.gnd1 260 *.VDD Encode1_tile_S_i26.vdd1 261 *.IN Encode1_tile_S_i26.DFF_to_Enc1inv 36 *.IN Encode1_tile_S_i26.DFF_to_Enc1 37 *.GND Encode1_tile_S_i26.gnd2 262 *.OUT Encode1_tile_S_i26.Enc1_to_Enc2 101 *.GND Encode1_tile_S_i27.gnd0 263 *.VDD Encode1_tile_S_i27.vdd0 264 *.GND Encode1_tile_S_i27.gnd1 265 *.VDD Encode1_tile_S_i27.vdd1 266 *.IN Encode1_tile_S_i27.DFF_to_Enc1inv 35 *.IN Encode1_tile_S_i27.DFF_to_Enc1 36 *.GND Encode1_tile_S_i27.gnd2 267 *.OUT Encode1_tile_S_i27.Enc1_to_Enc2 100 *.GND Encode1_tile_S_i28.gnd0 268 *.VDD Encode1_tile_S_i28.vdd0 269 *.GND Encode1_tile_S_i28.gnd1 270 *.VDD Encode1_tile_S_i28.vdd1 271 *.IN Encode1_tile_S_i28.DFF_to_Enc1inv 34 *.IN Encode1_tile_S_i28.DFF_to_Enc1 35 *.GND Encode1_tile_S_i28.gnd2 272 *.OUT Encode1_tile_S_i28.Enc1_to_Enc2 99 *.GND Encode1_tile_S_i29.gnd0 273 *.VDD Encode1_tile_S_i29.vdd0 274 *.GND Encode1_tile_S_i29.gnd1 275 *.VDD Encode1_tile_S_i29.vdd1 276 *.IN Encode1_tile_S_i29.DFF_to_Enc1inv 33 *.IN Encode1_tile_S_i29.DFF_to_Enc1 34 *.GND Encode1_tile_S_i29.gnd2 277 *.OUT Encode1_tile_S_i29.Enc1_to_Enc2 98 *.GND Encode1_tile_S_i30.gnd0 278 *.VDD Encode1_tile_S_i30.vdd0 279 *.GND Encode1_tile_S_i30.gnd1 280 *.VDD Encode1_tile_S_i30.vdd1 281 *.IN Encode1_tile_S_i30.DFF_to_Enc1inv 32 *.IN Encode1_tile_S_i30.DFF_to_Enc1 33 *.GND Encode1_tile_S_i30.gnd2 282 *.OUT Encode1_tile_S_i30.Enc1_to_Enc2 97 *.GND Encode1_tile_S_i31.gnd0 283 *.VDD Encode1_tile_S_i31.vdd0 284 *.GND Encode1_tile_S_i31.gnd1 285 *.VDD Encode1_tile_S_i31.vdd1 286 *.IN Encode1_tile_S_i31.DFF_to_Enc1inv 31 *.IN Encode1_tile_S_i31.DFF_to_Enc1 32 *.GND Encode1_tile_S_i31.gnd2 287 *.OUT Encode1_tile_S_i31.Enc1_to_Enc2 96 *.GND Encode1_tile_S_i32.gnd0 288 *.VDD Encode1_tile_S_i32.vdd0 289 *.GND Encode1_tile_S_i32.gnd1 290 *.VDD Encode1_tile_S_i32.vdd1 291 *.IN Encode1_tile_S_i32.DFF_to_Enc1inv 30 *.IN Encode1_tile_S_i32.DFF_to_Enc1 31 *.GND Encode1_tile_S_i32.gnd2 292 *.OUT Encode1_tile_S_i32.Enc1_to_Enc2 95 *.GND Encode1_tile_S_i33.gnd0 293 *.VDD Encode1_tile_S_i33.vdd0 294 *.GND Encode1_tile_S_i33.gnd1 295 *.VDD Encode1_tile_S_i33.vdd1 296 *.IN Encode1_tile_S_i33.DFF_to_Enc1inv 29 *.IN Encode1_tile_S_i33.DFF_to_Enc1 30 *.GND Encode1_tile_S_i33.gnd2 297 *.OUT Encode1_tile_S_i33.Enc1_to_Enc2 94 *.GND Encode1_tile_S_i34.gnd0 298 *.VDD Encode1_tile_S_i34.vdd0 299 *.GND Encode1_tile_S_i34.gnd1 300 *.VDD Encode1_tile_S_i34.vdd1 301 *.IN Encode1_tile_S_i34.DFF_to_Enc1inv 28 *.IN Encode1_tile_S_i34.DFF_to_Enc1 29 *.GND Encode1_tile_S_i34.gnd2 302 *.OUT Encode1_tile_S_i34.Enc1_to_Enc2 93 *.GND Encode1_tile_S_i35.gnd0 303 *.VDD Encode1_tile_S_i35.vdd0 304 *.GND Encode1_tile_S_i35.gnd1 305 *.VDD Encode1_tile_S_i35.vdd1 306 *.IN Encode1_tile_S_i35.DFF_to_Enc1inv 27 *.IN Encode1_tile_S_i35.DFF_to_Enc1 28 *.GND Encode1_tile_S_i35.gnd2 307 *.OUT Encode1_tile_S_i35.Enc1_to_Enc2 92 *.GND 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Encode1_tile_S_i39.vdd1 326 *.IN Encode1_tile_S_i39.DFF_to_Enc1inv 23 *.IN Encode1_tile_S_i39.DFF_to_Enc1 24 *.GND Encode1_tile_S_i39.gnd2 327 *.OUT Encode1_tile_S_i39.Enc1_to_Enc2 88 *.GND Encode1_tile_S_i40.gnd0 328 *.VDD Encode1_tile_S_i40.vdd0 329 *.GND Encode1_tile_S_i40.gnd1 330 *.VDD Encode1_tile_S_i40.vdd1 331 *.IN Encode1_tile_S_i40.DFF_to_Enc1inv 22 *.IN Encode1_tile_S_i40.DFF_to_Enc1 23 *.GND Encode1_tile_S_i40.gnd2 332 *.OUT Encode1_tile_S_i40.Enc1_to_Enc2 87 *.GND Encode1_tile_S_i41.gnd0 333 *.VDD Encode1_tile_S_i41.vdd0 334 *.GND Encode1_tile_S_i41.gnd1 335 *.VDD Encode1_tile_S_i41.vdd1 336 *.IN Encode1_tile_S_i41.DFF_to_Enc1inv 21 *.IN Encode1_tile_S_i41.DFF_to_Enc1 22 *.GND Encode1_tile_S_i41.gnd2 337 *.OUT Encode1_tile_S_i41.Enc1_to_Enc2 86 *.GND Encode1_tile_S_i42.gnd0 338 *.VDD Encode1_tile_S_i42.vdd0 339 *.GND Encode1_tile_S_i42.gnd1 340 *.VDD Encode1_tile_S_i42.vdd1 341 *.IN Encode1_tile_S_i42.DFF_to_Enc1inv 20 *.IN Encode1_tile_S_i42.DFF_to_Enc1 21 *.GND Encode1_tile_S_i42.gnd2 342 *.OUT Encode1_tile_S_i42.Enc1_to_Enc2 85 *.GND Encode1_tile_S_i43.gnd0 343 *.VDD Encode1_tile_S_i43.vdd0 344 *.GND Encode1_tile_S_i43.gnd1 345 *.VDD Encode1_tile_S_i43.vdd1 346 *.IN Encode1_tile_S_i43.DFF_to_Enc1inv 19 *.IN Encode1_tile_S_i43.DFF_to_Enc1 20 *.GND Encode1_tile_S_i43.gnd2 347 *.OUT Encode1_tile_S_i43.Enc1_to_Enc2 84 *.GND Encode1_tile_S_i44.gnd0 348 *.VDD Encode1_tile_S_i44.vdd0 349 *.GND Encode1_tile_S_i44.gnd1 350 *.VDD Encode1_tile_S_i44.vdd1 351 *.IN Encode1_tile_S_i44.DFF_to_Enc1inv 18 *.IN Encode1_tile_S_i44.DFF_to_Enc1 19 *.GND Encode1_tile_S_i44.gnd2 352 *.OUT Encode1_tile_S_i44.Enc1_to_Enc2 83 *.GND Encode1_tile_S_i45.gnd0 353 *.VDD Encode1_tile_S_i45.vdd0 354 *.GND Encode1_tile_S_i45.gnd1 355 *.VDD Encode1_tile_S_i45.vdd1 356 *.IN Encode1_tile_S_i45.DFF_to_Enc1inv 17 *.IN Encode1_tile_S_i45.DFF_to_Enc1 18 *.GND Encode1_tile_S_i45.gnd2 357 *.OUT Encode1_tile_S_i45.Enc1_to_Enc2 82 *.GND Encode1_tile_S_i46.gnd0 358 *.VDD Encode1_tile_S_i46.vdd0 359 *.GND Encode1_tile_S_i46.gnd1 360 *.VDD Encode1_tile_S_i46.vdd1 361 *.IN Encode1_tile_S_i46.DFF_to_Enc1inv 16 *.IN Encode1_tile_S_i46.DFF_to_Enc1 17 *.GND Encode1_tile_S_i46.gnd2 362 *.OUT Encode1_tile_S_i46.Enc1_to_Enc2 81 *.GND Encode1_tile_S_i47.gnd0 363 *.VDD Encode1_tile_S_i47.vdd0 364 *.GND Encode1_tile_S_i47.gnd1 365 *.VDD Encode1_tile_S_i47.vdd1 366 *.IN Encode1_tile_S_i47.DFF_to_Enc1inv 15 *.IN Encode1_tile_S_i47.DFF_to_Enc1 16 *.GND Encode1_tile_S_i47.gnd2 367 *.OUT Encode1_tile_S_i47.Enc1_to_Enc2 80 *.GND Encode1_tile_S_i48.gnd0 368 *.VDD Encode1_tile_S_i48.vdd0 369 *.GND Encode1_tile_S_i48.gnd1 370 *.VDD Encode1_tile_S_i48.vdd1 371 *.IN Encode1_tile_S_i48.DFF_to_Enc1inv 14 *.IN Encode1_tile_S_i48.DFF_to_Enc1 15 *.GND Encode1_tile_S_i48.gnd2 372 *.OUT Encode1_tile_S_i48.Enc1_to_Enc2 79 *.GND Encode1_tile_S_i49.gnd0 373 *.VDD Encode1_tile_S_i49.vdd0 374 *.GND Encode1_tile_S_i49.gnd1 375 *.VDD Encode1_tile_S_i49.vdd1 376 *.IN Encode1_tile_S_i49.DFF_to_Enc1inv 13 *.IN Encode1_tile_S_i49.DFF_to_Enc1 14 *.GND Encode1_tile_S_i49.gnd2 377 *.OUT Encode1_tile_S_i49.Enc1_to_Enc2 78 *.GND Encode1_tile_S_i50.gnd0 378 *.VDD Encode1_tile_S_i50.vdd0 379 *.GND Encode1_tile_S_i50.gnd1 380 *.VDD Encode1_tile_S_i50.vdd1 381 *.IN Encode1_tile_S_i50.DFF_to_Enc1inv 12 *.IN Encode1_tile_S_i50.DFF_to_Enc1 13 *.GND Encode1_tile_S_i50.gnd2 382 *.OUT Encode1_tile_S_i50.Enc1_to_Enc2 77 *.GND Encode1_tile_S_i51.gnd0 383 *.VDD Encode1_tile_S_i51.vdd0 384 *.GND Encode1_tile_S_i51.gnd1 385 *.VDD Encode1_tile_S_i51.vdd1 386 *.IN Encode1_tile_S_i51.DFF_to_Enc1inv 11 *.IN Encode1_tile_S_i51.DFF_to_Enc1 12 *.GND Encode1_tile_S_i51.gnd2 387 *.OUT Encode1_tile_S_i51.Enc1_to_Enc2 76 *.GND Encode1_tile_S_i52.gnd0 388 *.VDD Encode1_tile_S_i52.vdd0 389 *.GND Encode1_tile_S_i52.gnd1 390 *.VDD Encode1_tile_S_i52.vdd1 391 *.IN Encode1_tile_S_i52.DFF_to_Enc1inv 10 *.IN Encode1_tile_S_i52.DFF_to_Enc1 11 *.GND Encode1_tile_S_i52.gnd2 392 *.OUT Encode1_tile_S_i52.Enc1_to_Enc2 75 *.GND Encode1_tile_S_i53.gnd0 393 *.VDD Encode1_tile_S_i53.vdd0 394 *.GND Encode1_tile_S_i53.gnd1 395 *.VDD Encode1_tile_S_i53.vdd1 396 *.IN Encode1_tile_S_i53.DFF_to_Enc1inv 9 *.IN Encode1_tile_S_i53.DFF_to_Enc1 10 *.GND Encode1_tile_S_i53.gnd2 397 *.OUT Encode1_tile_S_i53.Enc1_to_Enc2 74 *.GND Encode1_tile_S_i54.gnd0 398 *.VDD Encode1_tile_S_i54.vdd0 399 *.GND Encode1_tile_S_i54.gnd1 400 *.VDD Encode1_tile_S_i54.vdd1 401 *.IN Encode1_tile_S_i54.DFF_to_Enc1inv 8 *.IN Encode1_tile_S_i54.DFF_to_Enc1 9 *.GND Encode1_tile_S_i54.gnd2 402 *.OUT Encode1_tile_S_i54.Enc1_to_Enc2 73 *.GND Encode1_tile_S_i55.gnd0 403 *.VDD Encode1_tile_S_i55.vdd0 404 *.GND Encode1_tile_S_i55.gnd1 405 *.VDD Encode1_tile_S_i55.vdd1 406 *.IN Encode1_tile_S_i55.DFF_to_Enc1inv 7 *.IN Encode1_tile_S_i55.DFF_to_Enc1 8 *.GND Encode1_tile_S_i55.gnd2 407 *.OUT Encode1_tile_S_i55.Enc1_to_Enc2 72 *.GND Encode1_tile_S_i56.gnd0 408 *.VDD Encode1_tile_S_i56.vdd0 409 *.GND Encode1_tile_S_i56.gnd1 410 *.VDD Encode1_tile_S_i56.vdd1 411 *.IN Encode1_tile_S_i56.DFF_to_Enc1inv 6 *.IN Encode1_tile_S_i56.DFF_to_Enc1 7 *.GND Encode1_tile_S_i56.gnd2 412 *.OUT Encode1_tile_S_i56.Enc1_to_Enc2 71 *.GND Encode1_tile_S_i57.gnd0 413 *.VDD Encode1_tile_S_i57.vdd0 414 *.GND Encode1_tile_S_i57.gnd1 415 *.VDD Encode1_tile_S_i57.vdd1 416 *.IN Encode1_tile_S_i57.DFF_to_Enc1inv 5 *.IN Encode1_tile_S_i57.DFF_to_Enc1 6 *.GND Encode1_tile_S_i57.gnd2 417 *.OUT Encode1_tile_S_i57.Enc1_to_Enc2 70 *.GND Encode1_tile_S_i58.gnd0 418 *.VDD Encode1_tile_S_i58.vdd0 419 *.GND Encode1_tile_S_i58.gnd1 420 *.VDD Encode1_tile_S_i58.vdd1 421 *.IN Encode1_tile_S_i58.DFF_to_Enc1inv 4 *.IN Encode1_tile_S_i58.DFF_to_Enc1 5 *.GND Encode1_tile_S_i58.gnd2 422 *.OUT Encode1_tile_S_i58.Enc1_to_Enc2 69 *.GND Encode1_tile_S_i59.gnd0 423 *.VDD Encode1_tile_S_i59.vdd0 424 *.GND Encode1_tile_S_i59.gnd1 425 *.VDD Encode1_tile_S_i59.vdd1 426 *.IN Encode1_tile_S_i59.DFF_to_Enc1inv 3 *.IN Encode1_tile_S_i59.DFF_to_Enc1 4 *.GND Encode1_tile_S_i59.gnd2 427 *.OUT Encode1_tile_S_i59.Enc1_to_Enc2 68 *.GND Encode1_tile_S_i60.gnd0 428 *.VDD Encode1_tile_S_i60.vdd0 429 *.GND Encode1_tile_S_i60.gnd1 430 *.VDD Encode1_tile_S_i60.vdd1 431 *.IN Encode1_tile_S_i60.DFF_to_Enc1inv 2 *.IN Encode1_tile_S_i60.DFF_to_Enc1 3 *.GND Encode1_tile_S_i60.gnd2 432 *.OUT Encode1_tile_S_i60.Enc1_to_Enc2 67 *.GND Encode1_tile_S_i61.gnd0 433 *.VDD Encode1_tile_S_i61.vdd0 434 *.GND Encode1_tile_S_i61.gnd1 435 *.VDD Encode1_tile_S_i61.vdd1 436 *.IN Encode1_tile_S_i61.DFF_to_Enc1inv 1 *.IN Encode1_tile_S_i61.DFF_to_Enc1 2 *.GND Encode1_tile_S_i61.gnd2 437 *.OUT Encode1_tile_S_i61.Enc1_to_Enc2 66 *.GND Encode1_tile_S_i62.gnd0 438 *.VDD Encode1_tile_S_i62.vdd0 439 *.GND Encode1_tile_S_i62.gnd1 440 *.VDD Encode1_tile_S_i62.vdd1 441 *.IN Encode1_tile_S_i62.DFF_to_Enc1inv 64 *.IN Encode1_tile_S_i62.DFF_to_Enc1 1 *.GND Encode1_tile_S_i62.gnd2 442 *.OUT Encode1_tile_S_i62.Enc1_to_Enc2 65 *.Vnwell 570 0 5 *.Vbulk 569 0 0 *.Vpwell 571 0 0 *.Vbulk 569 0 5 VGND591 128 0 0 VVDD592 129 0 5.00 VGND592 130 0 0 VVDD593 131 0 5.00 VGND593 132 0 0 VGND594 133 0 0 VVDD594 134 0 5.00 VGND595 135 0 0 VVDD595 136 0 5.00 VGND596 137 0 0 VGND597 138 0 0 VVDD596 139 0 5.00 VGND598 140 0 0 VVDD597 141 0 5.00 VGND599 142 0 0 VGND600 143 0 0 VVDD598 144 0 5.00 VGND601 145 0 0 VVDD599 146 0 5.00 VGND602 147 0 0 VGND603 148 0 0 VVDD600 149 0 5.00 VGND604 150 0 0 VVDD601 151 0 5.00 VGND605 152 0 0 VGND606 153 0 0 VVDD602 154 0 5.00 VGND607 155 0 0 VVDD603 156 0 5.00 VGND608 157 0 0 VGND609 158 0 0 VVDD604 159 0 5.00 VGND610 160 0 0 VVDD605 161 0 5.00 VGND611 162 0 0 VGND612 163 0 0 VVDD606 164 0 5.00 VGND613 165 0 0 VVDD607 166 0 5.00 VGND614 167 0 0 VGND615 168 0 0 VVDD608 169 0 5.00 VGND616 170 0 0 VVDD609 171 0 5.00 VGND617 172 0 0 VGND618 173 0 0 VVDD610 174 0 5.00 VGND619 175 0 0 VVDD611 176 0 5.00 VGND620 177 0 0 VGND621 178 0 0 VVDD612 179 0 5.00 VGND622 180 0 0 VVDD613 181 0 5.00 VGND623 182 0 0 VGND624 183 0 0 VVDD614 184 0 5.00 VGND625 185 0 0 VVDD615 186 0 5.00 VGND626 187 0 0 VGND627 188 0 0 VVDD616 189 0 5.00 VGND628 190 0 0 VVDD617 191 0 5.00 VGND629 192 0 0 VGND630 193 0 0 VVDD618 194 0 5.00 VGND631 195 0 0 VVDD619 196 0 5.00 VGND632 197 0 0 VGND633 198 0 0 VVDD620 199 0 5.00 VGND634 200 0 0 VVDD621 201 0 5.00 VGND635 202 0 0 VGND636 203 0 0 VVDD622 204 0 5.00 VGND637 205 0 0 VVDD623 206 0 5.00 VGND638 207 0 0 VGND639 208 0 0 VVDD624 209 0 5.00 VGND640 210 0 0 VVDD625 211 0 5.00 VGND641 212 0 0 VGND642 213 0 0 VVDD626 214 0 5.00 VGND643 215 0 0 VVDD627 216 0 5.00 VGND644 217 0 0 VGND645 218 0 0 VVDD628 219 0 5.00 VGND646 220 0 0 VVDD629 221 0 5.00 VGND647 222 0 0 VGND648 223 0 0 VVDD630 224 0 5.00 VGND649 225 0 0 VVDD631 226 0 5.00 VGND650 227 0 0 VGND651 228 0 0 VVDD632 229 0 5.00 VGND652 230 0 0 VVDD633 231 0 5.00 VGND653 232 0 0 VGND654 233 0 0 VVDD634 234 0 5.00 VGND655 235 0 0 VVDD635 236 0 5.00 VGND656 237 0 0 VGND657 238 0 0 VVDD636 239 0 5.00 VGND658 240 0 0 VVDD637 241 0 5.00 VGND659 242 0 0 VGND660 243 0 0 VVDD638 244 0 5.00 VGND661 245 0 0 VVDD639 246 0 5.00 VGND662 247 0 0 VGND663 248 0 0 VVDD640 249 0 5.00 VGND664 250 0 0 VVDD641 251 0 5.00 VGND665 252 0 0 VGND666 253 0 0 VVDD642 254 0 5.00 VGND667 255 0 0 VVDD643 256 0 5.00 VGND668 257 0 0 VGND669 258 0 0 VVDD644 259 0 5.00 VGND670 260 0 0 VVDD645 261 0 5.00 VGND671 262 0 0 VGND672 263 0 0 VVDD646 264 0 5.00 VGND673 265 0 0 VVDD647 266 0 5.00 VGND674 267 0 0 VGND675 268 0 0 VVDD648 269 0 5.00 VGND676 270 0 0 VVDD649 271 0 5.00 VGND677 272 0 0 VGND678 273 0 0 VVDD650 274 0 5.00 VGND679 275 0 0 VVDD651 276 0 5.00 VGND680 277 0 0 VGND681 278 0 0 VVDD652 279 0 5.00 VGND682 280 0 0 VVDD653 281 0 5.00 VGND683 282 0 0 VGND684 283 0 0 VVDD654 284 0 5.00 VGND685 285 0 0 VVDD655 286 0 5.00 VGND686 287 0 0 VGND687 288 0 0 VVDD656 289 0 5.00 VGND688 290 0 0 VVDD657 291 0 5.00 VGND689 292 0 0 VGND690 293 0 0 VVDD658 294 0 5.00 VGND691 295 0 0 VVDD659 296 0 5.00 VGND692 297 0 0 VGND693 298 0 0 VVDD660 299 0 5.00 VGND694 300 0 0 VVDD661 301 0 5.00 VGND695 302 0 0 VGND696 303 0 0 VVDD662 304 0 5.00 VGND697 305 0 0 VVDD663 306 0 5.00 VGND698 307 0 0 VGND699 308 0 0 VVDD664 309 0 5.00 VGND700 310 0 0 VVDD665 311 0 5.00 VGND701 312 0 0 VGND702 313 0 0 VVDD666 314 0 5.00 VGND703 315 0 0 VVDD667 316 0 5.00 VGND704 317 0 0 VGND705 318 0 0 VVDD668 319 0 5.00 VGND706 320 0 0 VVDD669 321 0 5.00 VGND707 322 0 0 VGND708 323 0 0 VVDD670 324 0 5.00 VGND709 325 0 0 VVDD671 326 0 5.00 VGND710 327 0 0 VGND711 328 0 0 VVDD672 329 0 5.00 VGND712 330 0 0 VVDD673 331 0 5.00 VGND713 332 0 0 VGND714 333 0 0 VVDD674 334 0 5.00 VGND715 335 0 0 VVDD675 336 0 5.00 VGND716 337 0 0 VGND717 338 0 0 VVDD676 339 0 5.00 VGND718 340 0 0 VVDD677 341 0 5.00 VGND719 342 0 0 VGND720 343 0 0 VVDD678 344 0 5.00 VGND721 345 0 0 VVDD679 346 0 5.00 VGND722 347 0 0 VGND723 348 0 0 VVDD680 349 0 5.00 VGND724 350 0 0 VVDD681 351 0 5.00 VGND725 352 0 0 VGND726 353 0 0 VVDD682 354 0 5.00 VGND727 355 0 0 VVDD683 356 0 5.00 VGND728 357 0 0 VGND729 358 0 0 VVDD684 359 0 5.00 VGND730 360 0 0 VVDD685 361 0 5.00 VGND731 362 0 0 VGND732 363 0 0 VVDD686 364 0 5.00 VGND733 365 0 0 VVDD687 366 0 5.00 VGND734 367 0 0 VGND735 368 0 0 VVDD688 369 0 5.00 VGND736 370 0 0 VVDD689 371 0 5.00 VGND737 372 0 0 VGND738 373 0 0 VVDD690 374 0 5.00 VGND739 375 0 0 VVDD691 376 0 5.00 VGND740 377 0 0 VGND741 378 0 0 VVDD692 379 0 5.00 VGND742 380 0 0 VVDD693 381 0 5.00 VGND743 382 0 0 VGND744 383 0 0 VVDD694 384 0 5.00 VGND745 385 0 0 VVDD695 386 0 5.00 VGND746 387 0 0 VGND747 388 0 0 VVDD696 389 0 5.00 VGND748 390 0 0 VVDD697 391 0 5.00 VGND749 392 0 0 VGND750 393 0 0 VVDD698 394 0 5.00 VGND751 395 0 0 VVDD699 396 0 5.00 VGND752 397 0 0 VGND753 398 0 0 VVDD700 399 0 5.00 VGND754 400 0 0 VVDD701 401 0 5.00 VGND755 402 0 0 VGND756 403 0 0 VVDD702 404 0 5.00 VGND757 405 0 0 VVDD703 406 0 5.00 VGND758 407 0 0 VGND759 408 0 0 VVDD704 409 0 5.00 VGND760 410 0 0 VVDD705 411 0 5.00 VGND761 412 0 0 VGND762 413 0 0 VVDD706 414 0 5.00 VGND763 415 0 0 VVDD707 416 0 5.00 VGND764 417 0 0 VGND765 418 0 0 VVDD708 419 0 5.00 VGND766 420 0 0 VVDD709 421 0 5.00 VGND767 422 0 0 VGND768 423 0 0 VVDD710 424 0 5.00 VGND769 425 0 0 VVDD711 426 0 5.00 VGND770 427 0 0 VGND771 428 0 0 VVDD712 429 0 5.00 VGND772 430 0 0 VVDD713 431 0 5.00 VGND773 432 0 0 VGND774 433 0 0 VVDD714 434 0 5.00 VGND775 435 0 0 VVDD715 436 0 5.00 VGND776 437 0 0 VGND777 438 0 0 VVDD716 439 0 5.00 VGND778 440 0 0 VVDD717 441 0 5.00 VGND779 442 0 0 *TEXT DFF_to_Enc1_[62] " "; *TEXT node0[62] " "; *TEXT node1[62] " "; *TEXT node2[62] " "; *TEXT node3[62] " "; *TEXT Dff_to_Enc1inv_[62] " "; *TEXT node6[62] " "; *TEXT node7[62] " "; *TEXT node8[62] " "; *TEXT node9[62] " "; *TEXT Enc1_to_Enc2_[62] " "; *TEXT node13[62] " "; *TEXT node14[62] " "; *TEXT node15[62] " "; *TEXT node16[62] " "; *TEXT w0.[1][0] "0"; *TEXT w1.[1][0] "1"; *TEXT w3.[1][0] "2"; *TEXT w4.[1][0] "3"; *TEXT w5.[1][0] "4"; *TEXT w6.[1][0] "5"; *TEXT w7.[1][0] "6"; *TEXT w8.[1][0] "7"; *TEXT w9.[1][0] "8"; *TEXT w10.[1][0] "9"; *TEXT w11.[1][0] "10"; *TEXT w12.[1][0] "11"; *TEXT w13.[1][0] "12"; *TEXT w14.[1][0] "13"; *TEXT w15.[1][0] "14"; *TEXT w16.[1][0] "15"; *TEXT w134.[1][0] "16"; *TEXT w18.[1][0] "17"; *TEXT w19.[1][0] "18"; *TEXT w20.[1][0] "19"; *TEXT w21.[1][0] "20"; *TEXT w22.[1][0] "21"; *TEXT w23.[1][0] "22"; *TEXT w24.[1][0] "23"; *TEXT w25.[1][0] "24"; *TEXT w26.[1][0] "25"; *TEXT w27.[1][0] "26"; *TEXT w28.[1][0] "27"; *TEXT w29.[1][0] "28"; *TEXT w30.[1][0] "29"; *TEXT w31.[1][0] "30"; *TEXT w32.[1][0] "31"; *TEXT w192.[1][0] "32"; *TEXT w34.[1][0] "33"; *TEXT w35.[1][0] "34"; *TEXT w36.[1][0] "35"; *TEXT w37.[1][0] "36"; *TEXT w38.[1][0] "37"; *TEXT w39.[1][0] "38"; *TEXT w40.[1][0] "39"; *TEXT w41.[1][0] "40"; *TEXT w42.[1][0] "41"; *TEXT w43.[1][0] "42"; *TEXT w44.[1][0] "43"; *TEXT w45.[1][0] "44"; *TEXT w46.[1][0] "45"; *TEXT w47.[1][0] "46"; *TEXT w48.[1][0] "47"; *TEXT w194.[1][0] "48"; *TEXT w50.[1][0] "49"; *TEXT w51.[1][0] "50"; *TEXT w52.[1][0] "51"; *TEXT w53.[1][0] "52"; *TEXT w54.[1][0] "53"; *TEXT w55.[1][0] "54"; *TEXT w56.[1][0] "55"; *TEXT w57.[1][0] "56"; *TEXT w58.[1][0] "57"; *TEXT w59.[1][0] "58"; *TEXT w60.[1][0] "59"; *TEXT w61.[1][0] "60"; *TEXT w62.[1][0] "61"; *TEXT w63.[1][0] "62"; *TEXT w64.[1][0] "0"; *TEXT w65.[1][0] "1"; *TEXT w66.[1][0] "2"; *TEXT w67.[1][0] "3"; *TEXT w68.[1][0] "4"; *TEXT w69.[1][0] "5"; *TEXT w70.[1][0] "6"; *TEXT w71.[1][0] "7"; *TEXT w72.[1][0] "8"; *TEXT w73.[1][0] "9"; *TEXT w74.[1][0] "10"; *TEXT w75.[1][0] "11"; *TEXT w76.[1][0] "12"; *TEXT w77.[1][0] "13"; *TEXT w78.[1][0] "14"; *TEXT w79.[1][0] "15"; *TEXT w80.[1][0] "16"; *TEXT w81.[1][0] "17"; *TEXT w82.[1][0] "18"; *TEXT w83.[1][0] "19"; *TEXT w84.[1][0] "20"; *TEXT w85.[1][0] "21"; *TEXT w86.[1][0] "22"; *TEXT w87.[1][0] "23"; *TEXT w88.[1][0] "24"; *TEXT w89.[1][0] "25"; *TEXT w90.[1][0] "26"; *TEXT w91.[1][0] "27"; *TEXT w92.[1][0] "28"; *TEXT w93.[1][0] "29"; *TEXT w94.[1][0] "30"; *TEXT w95.[1][0] "31"; *TEXT w96.[1][0] "32"; *TEXT w97.[1][0] "33"; *TEXT w98.[1][0] "34"; *TEXT w99.[1][0] "35"; *TEXT w100.[1][0] "36"; *TEXT w101.[1][0] "37"; *TEXT w102.[1][0] "38"; *TEXT w103.[1][0] "39"; *TEXT w104.[1][0] "40"; *TEXT w105.[1][0] "41"; *TEXT w106.[1][0] "42"; *TEXT w107.[1][0] "43"; *TEXT w108.[1][0] "44"; *TEXT w109.[1][0] "45"; *TEXT w110.[1][0] "46"; *TEXT w111.[1][0] "47"; *TEXT w112.[1][0] "48"; *TEXT w113.[1][0] "49"; *TEXT w114.[1][0] "50"; *TEXT w115.[1][0] "51"; *TEXT w116.[1][0] "52"; *TEXT w117.[1][0] "53"; *TEXT w118.[1][0] "54"; *TEXT w119.[1][0] "55"; *TEXT w120.[1][0] "56"; *TEXT w121.[1][0] "57"; *TEXT w122.[1][0] "58"; *TEXT w123.[1][0] "59"; *TEXT w124.[1][0] "60"; *TEXT w125.[1][0] "61"; *TEXT w126.[1][0] "62"; *TEXT w127.[1][0] "0"; *TEXT w128.[1][0] "1"; *TEXT w129.[1][0] "2"; *TEXT w130.[1][0] "3"; *TEXT w131.[1][0] "4"; *TEXT w132.[1][0] "5"; *TEXT w133.[1][0] "6"; *TEXT w136.[1][0] "9"; *TEXT w137.[1][0] "7"; *TEXT w138.[1][0] "8"; *TEXT w139.[1][0] "10"; *TEXT w140.[1][0] "11"; *TEXT w141.[1][0] "12"; *TEXT w142.[1][0] "13"; *TEXT w143.[1][0] "14"; *TEXT w144.[1][0] "15"; *TEXT w145.[1][0] "16"; *TEXT w146.[1][0] "17"; *TEXT w147.[1][0] "18"; *TEXT w148.[1][0] "19"; *TEXT w149.[1][0] "20"; *TEXT w150.[1][0] "21"; *TEXT w151.[1][0] "22"; *TEXT w152.[1][0] "23"; *TEXT w153.[1][0] "24"; *TEXT w154.[1][0] "25"; *TEXT w155.[1][0] "26"; *TEXT w156.[1][0] "27"; *TEXT w157.[1][0] "28"; *TEXT w158.[1][0] "29"; *TEXT w159.[1][0] "30"; *TEXT w160.[1][0] "31"; *TEXT w161.[1][0] "32"; *TEXT w162.[1][0] "33"; *TEXT w163.[1][0] "34"; *TEXT w164.[1][0] "35"; *TEXT w165.[1][0] "36"; *TEXT w166.[1][0] "37"; *TEXT w167.[1][0] "38"; *TEXT w168.[1][0] "39"; *TEXT w169.[1][0] "40"; *TEXT w170.[1][0] "41"; *TEXT w171.[1][0] "42"; *TEXT w172.[1][0] "43"; *TEXT w173.[1][0] "44"; *TEXT w174.[1][0] "45"; *TEXT w175.[1][0] "46"; *TEXT w176.[1][0] "47"; *TEXT w177.[1][0] "48"; *TEXT w178.[1][0] "49"; *TEXT w179.[1][0] "50"; *TEXT w180.[1][0] "51"; *TEXT w181.[1][0] "52"; *TEXT w182.[1][0] "53"; *TEXT w183.[1][0] "54"; *TEXT w184.[1][0] "55"; *TEXT w185.[1][0] "56"; *TEXT w186.[1][0] "57"; *TEXT w187.[1][0] "58"; *TEXT w188.[1][0] "59"; *TEXT w189.[1][0] "60"; *TEXT w190.[1][0] "61"; *TEXT w191.[1][0] "62"; *TEXT "Encode1"; *TEXT w135.[1][0] "15"; *TEXT w193.[1][0] "31"; *TEXT w195.[1][0] "47"; .ENDS Encode1_S .SUBCKT Dff_Out_tile_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 24 25 Mtn0 16 14 6 25 TN W=4.00U L=0.80U Mtp0 17 13 16 24 TP W=3.20U L=0.80U Mtp1 7 14 17 24 TP W=3.20U L=0.80U Mtp2 8 17 18 24 TP W=3.20U L=0.80U Mtn1 19 16 5 25 TN W=2.00U L=0.80U Mtn2 18 13 19 25 TN W=2.00U L=0.80U Mtp3 9 18 20 24 TP W=3.20U L=0.80U Mtn3 20 19 4 25 TN W=2.00U L=0.80U Mtp4 10 20 21 24 TP W=3.20U L=0.80U Mtn4 21 20 1 25 TN W=2.00U L=0.80U Mtp5 11 21 22 24 TP W=6.40U L=0.80U Mtn6 22 21 2 25 TN W=4.00U L=0.80U Mtp6 12 22 15 24 TP W=12.80U L=0.80U Mtn7 15 22 3 25 TN W=8.00U L=0.80U *.GND gnd0 1 *.GND gnd1 2 *.GND gnd2 3 *.GND gnd3 4 *.GND gnd4 5 *.GND gnd5 6 *.VDD vdd0 7 *.VDD vdd1 8 *.VDD vdd2 9 *.VDD vdd3 10 *.VDD vdd4 11 *.VDD vdd5 12 *.IN HIT 13 *.IN D_in 14 *.OUT Bit 15 *.Vnwell 24 0 5 *.Vbulk 23 0 0 *.Vpwell 25 0 0 *.Vbulk 23 0 5 *TEXT tn0 " "; *TEXT tp0 " "; *TEXT tp1 " "; *TEXT tp2 " "; *TEXT tn1 " "; *TEXT tn2 " "; *TEXT tp3 " "; *TEXT tn3 " "; *TEXT tp4 " "; *TEXT tn4 " "; *TEXT tp5 " "; *TEXT tn6 " "; *TEXT tp6 " "; *TEXT tn7 " "; *TEXT "Dff_Out_tile"; *TEXT "Note: the following redundant terminals have been removed: *DStrobe2, Dstrobe_poly"; .ENDS Dff_Out_tile_S .SUBCKT OutLatch_S 1 2 3 4 5 6 7 8 9 10 11 12 13 129 130 XDff_Out_tile_S_i0 14 15 16 17 18 19 20 21 22 23 24 25 7 1 8 129 130 + Dff_Out_tile_S XDff_Out_tile_S_i1 26 27 28 29 30 31 32 33 34 35 36 37 7 2 9 129 130 + Dff_Out_tile_S XDff_Out_tile_S_i2 38 39 40 41 42 43 44 45 46 47 48 49 7 3 10 129 130 + Dff_Out_tile_S XDff_Out_tile_S_i3 50 51 52 53 54 55 56 57 58 59 60 61 7 4 11 129 130 + Dff_Out_tile_S XDff_Out_tile_S_i4 62 63 64 65 66 67 68 69 70 71 72 73 7 5 12 129 130 + Dff_Out_tile_S XDff_Out_tile_S_i5 74 75 76 77 78 79 80 81 82 83 84 85 7 6 13 129 130 + Dff_Out_tile_S *.IN D_in[5] 1 *.IN D_in[4] 2 *.IN D_in[3] 3 *.IN D_in[2] 4 *.IN D_in[1] 5 *.IN D_in[0] 6 *.IN HIT_5 7 *.OUT Bit[5] 8 *.OUT Bit[4] 9 *.OUT Bit[3] 10 *.OUT Bit[2] 11 *.OUT Bit[1] 12 *.OUT Bit[0] 13 *.GND Dff_Out_tile_S_i0.gnd0 14 *.GND Dff_Out_tile_S_i0.gnd1 15 *.GND Dff_Out_tile_S_i0.gnd2 16 *.GND Dff_Out_tile_S_i0.gnd3 17 *.GND Dff_Out_tile_S_i0.gnd4 18 *.GND Dff_Out_tile_S_i0.gnd5 19 *.VDD Dff_Out_tile_S_i0.vdd0 20 *.VDD Dff_Out_tile_S_i0.vdd1 21 *.VDD Dff_Out_tile_S_i0.vdd2 22 *.VDD Dff_Out_tile_S_i0.vdd3 23 *.VDD Dff_Out_tile_S_i0.vdd4 24 *.VDD Dff_Out_tile_S_i0.vdd5 25 *.IN Dff_Out_tile_S_i0.HIT 7 *.IN Dff_Out_tile_S_i0.D_in 1 *.OUT Dff_Out_tile_S_i0.Bit 8 *.GND Dff_Out_tile_S_i1.gnd0 26 *.GND Dff_Out_tile_S_i1.gnd1 27 *.GND Dff_Out_tile_S_i1.gnd2 28 *.GND Dff_Out_tile_S_i1.gnd3 29 *.GND Dff_Out_tile_S_i1.gnd4 30 *.GND Dff_Out_tile_S_i1.gnd5 31 *.VDD Dff_Out_tile_S_i1.vdd0 32 *.VDD Dff_Out_tile_S_i1.vdd1 33 *.VDD Dff_Out_tile_S_i1.vdd2 34 *.VDD Dff_Out_tile_S_i1.vdd3 35 *.VDD Dff_Out_tile_S_i1.vdd4 36 *.VDD Dff_Out_tile_S_i1.vdd5 37 *.IN Dff_Out_tile_S_i1.HIT 7 *.IN Dff_Out_tile_S_i1.D_in 2 *.OUT Dff_Out_tile_S_i1.Bit 9 *.GND Dff_Out_tile_S_i2.gnd0 38 *.GND Dff_Out_tile_S_i2.gnd1 39 *.GND Dff_Out_tile_S_i2.gnd2 40 *.GND Dff_Out_tile_S_i2.gnd3 41 *.GND Dff_Out_tile_S_i2.gnd4 42 *.GND Dff_Out_tile_S_i2.gnd5 43 *.VDD Dff_Out_tile_S_i2.vdd0 44 *.VDD Dff_Out_tile_S_i2.vdd1 45 *.VDD Dff_Out_tile_S_i2.vdd2 46 *.VDD Dff_Out_tile_S_i2.vdd3 47 *.VDD Dff_Out_tile_S_i2.vdd4 48 *.VDD Dff_Out_tile_S_i2.vdd5 49 *.IN Dff_Out_tile_S_i2.HIT 7 *.IN Dff_Out_tile_S_i2.D_in 3 *.OUT Dff_Out_tile_S_i2.Bit 10 *.GND Dff_Out_tile_S_i3.gnd0 50 *.GND Dff_Out_tile_S_i3.gnd1 51 *.GND Dff_Out_tile_S_i3.gnd2 52 *.GND Dff_Out_tile_S_i3.gnd3 53 *.GND Dff_Out_tile_S_i3.gnd4 54 *.GND Dff_Out_tile_S_i3.gnd5 55 *.VDD Dff_Out_tile_S_i3.vdd0 56 *.VDD Dff_Out_tile_S_i3.vdd1 57 *.VDD Dff_Out_tile_S_i3.vdd2 58 *.VDD Dff_Out_tile_S_i3.vdd3 59 *.VDD Dff_Out_tile_S_i3.vdd4 60 *.VDD Dff_Out_tile_S_i3.vdd5 61 *.IN Dff_Out_tile_S_i3.HIT 7 *.IN Dff_Out_tile_S_i3.D_in 4 *.OUT Dff_Out_tile_S_i3.Bit 11 *.GND Dff_Out_tile_S_i4.gnd0 62 *.GND Dff_Out_tile_S_i4.gnd1 63 *.GND Dff_Out_tile_S_i4.gnd2 64 *.GND Dff_Out_tile_S_i4.gnd3 65 *.GND Dff_Out_tile_S_i4.gnd4 66 *.GND Dff_Out_tile_S_i4.gnd5 67 *.VDD Dff_Out_tile_S_i4.vdd0 68 *.VDD Dff_Out_tile_S_i4.vdd1 69 *.VDD Dff_Out_tile_S_i4.vdd2 70 *.VDD Dff_Out_tile_S_i4.vdd3 71 *.VDD Dff_Out_tile_S_i4.vdd4 72 *.VDD Dff_Out_tile_S_i4.vdd5 73 *.IN Dff_Out_tile_S_i4.HIT 7 *.IN Dff_Out_tile_S_i4.D_in 5 *.OUT Dff_Out_tile_S_i4.Bit 12 *.GND Dff_Out_tile_S_i5.gnd0 74 *.GND Dff_Out_tile_S_i5.gnd1 75 *.GND Dff_Out_tile_S_i5.gnd2 76 *.GND Dff_Out_tile_S_i5.gnd3 77 *.GND Dff_Out_tile_S_i5.gnd4 78 *.GND Dff_Out_tile_S_i5.gnd5 79 *.VDD Dff_Out_tile_S_i5.vdd0 80 *.VDD Dff_Out_tile_S_i5.vdd1 81 *.VDD Dff_Out_tile_S_i5.vdd2 82 *.VDD Dff_Out_tile_S_i5.vdd3 83 *.VDD Dff_Out_tile_S_i5.vdd4 84 *.VDD Dff_Out_tile_S_i5.vdd5 85 *.IN Dff_Out_tile_S_i5.HIT 7 *.IN Dff_Out_tile_S_i5.D_in 6 *.OUT Dff_Out_tile_S_i5.Bit 13 *.Vnwell 129 0 5 *.Vbulk 128 0 0 *.Vpwell 130 0 0 *.Vbulk 128 0 5 VGND780 14 0 0 VGND781 15 0 0 VGND782 16 0 0 VGND783 17 0 0 VGND784 18 0 0 VGND785 19 0 0 VVDD718 20 0 5.00 VVDD719 21 0 5.00 VVDD720 22 0 5.00 VVDD721 23 0 5.00 VVDD722 24 0 5.00 VVDD723 25 0 5.00 VGND786 26 0 0 VGND787 27 0 0 VGND788 28 0 0 VGND789 29 0 0 VGND790 30 0 0 VGND791 31 0 0 VVDD724 32 0 5.00 VVDD725 33 0 5.00 VVDD726 34 0 5.00 VVDD727 35 0 5.00 VVDD728 36 0 5.00 VVDD729 37 0 5.00 VGND792 38 0 0 VGND793 39 0 0 VGND794 40 0 0 VGND795 41 0 0 VGND796 42 0 0 VGND797 43 0 0 VVDD730 44 0 5.00 VVDD731 45 0 5.00 VVDD732 46 0 5.00 VVDD733 47 0 5.00 VVDD734 48 0 5.00 VVDD735 49 0 5.00 VGND798 50 0 0 VGND799 51 0 0 VGND800 52 0 0 VGND801 53 0 0 VGND802 54 0 0 VGND803 55 0 0 VVDD736 56 0 5.00 VVDD737 57 0 5.00 VVDD738 58 0 5.00 VVDD739 59 0 5.00 VVDD740 60 0 5.00 VVDD741 61 0 5.00 VGND804 62 0 0 VGND805 63 0 0 VGND806 64 0 0 VGND807 65 0 0 VGND808 66 0 0 VGND809 67 0 0 VVDD742 68 0 5.00 VVDD743 69 0 5.00 VVDD744 70 0 5.00 VVDD745 71 0 5.00 VVDD746 72 0 5.00 VVDD747 73 0 5.00 VGND810 74 0 0 VGND811 75 0 0 VGND812 76 0 0 VGND813 77 0 0 VGND814 78 0 0 VGND815 79 0 0 VVDD748 80 0 5.00 VVDD749 81 0 5.00 VVDD750 82 0 5.00 VVDD751 83 0 5.00 VVDD752 84 0 5.00 VVDD753 85 0 5.00 *TEXT D_in[5] " "; *TEXT node0[5] " "; *TEXT w0.[1][0] "0"; *TEXT w1.[1][0] "1"; *TEXT w2.[1][0] "2"; *TEXT w3.[1][0] "3"; *TEXT w4.[1][0] "4"; *TEXT w5.[1][0] "5"; *TEXT HIT_5 " "; *TEXT Bit[5] " "; *TEXT node1[5] " "; *TEXT w6.[1][0] "0"; *TEXT w7.[1][0] "1"; *TEXT w8.[1][0] "2"; *TEXT w9.[1][0] "3"; *TEXT w10.[1][0] "4"; *TEXT w11.[1][0] "5"; *TEXT "OutLatch"; *TEXT "Note: the following redundant terminals have been removed: *Dstrobe_poly_5, Dstrobe_poly_0, HIT_0"; .ENDS OutLatch_S .SUBCKT Encode2c_tile_S 1 2 3 6 Mtn0 2 3 1 6 TN W=1.20U L=4.00U *.GND gnd0 1 *.OUT out0 2 *.VDD vdd0 3 *.Vpwell 6 0 0 *.Vbulk 4 0 5 *TEXT tn0 " "; *TEXT "Encode2c_tile"; .ENDS Encode2c_tile_S .SUBCKT Encode2c_S 1 2 3 4 5 6 21 XEncode2c_tile_S_i0 7 6 8 21 Encode2c_tile_S XEncode2c_tile_S_i1 9 5 10 21 Encode2c_tile_S XEncode2c_tile_S_i2 11 4 12 21 Encode2c_tile_S XEncode2c_tile_S_i3 13 3 14 21 Encode2c_tile_S XEncode2c_tile_S_i4 15 2 16 21 Encode2c_tile_S XEncode2c_tile_S_i5 17 1 18 21 Encode2c_tile_S *.OUT out0[5] 1 *.OUT out0[4] 2 *.OUT out0[3] 3 *.OUT out0[2] 4 *.OUT out0[1] 5 *.OUT out0[0] 6 *.GND Encode2c_tile_S_i0.gnd0 7 *.OUT Encode2c_tile_S_i0.out0 6 *.VDD Encode2c_tile_S_i0.vdd0 8 *.GND Encode2c_tile_S_i1.gnd0 9 *.OUT Encode2c_tile_S_i1.out0 5 *.VDD Encode2c_tile_S_i1.vdd0 10 *.GND Encode2c_tile_S_i2.gnd0 11 *.OUT Encode2c_tile_S_i2.out0 4 *.VDD Encode2c_tile_S_i2.vdd0 12 *.GND Encode2c_tile_S_i3.gnd0 13 *.OUT Encode2c_tile_S_i3.out0 3 *.VDD Encode2c_tile_S_i3.vdd0 14 *.GND Encode2c_tile_S_i4.gnd0 15 *.OUT Encode2c_tile_S_i4.out0 2 *.VDD Encode2c_tile_S_i4.vdd0 16 *.GND Encode2c_tile_S_i5.gnd0 17 *.OUT Encode2c_tile_S_i5.out0 1 *.VDD Encode2c_tile_S_i5.vdd0 18 *.Vpwell 21 0 0 *.Vbulk 19 0 5 VGND816 7 0 0 VVDD754 8 0 5.00 VGND817 9 0 0 VVDD755 10 0 5.00 VGND818 11 0 0 VVDD756 12 0 5.00 VGND819 13 0 0 VVDD757 14 0 5.00 VGND820 15 0 0 VVDD758 16 0 5.00 VGND821 17 0 0 VVDD759 18 0 5.00 *TEXT out0[5] " "; *TEXT node0[5] " "; *TEXT node1[5] " "; *TEXT w0.[1][0] "0"; *TEXT w1.[1][0] "1"; *TEXT w2.[1][0] "2"; *TEXT w3.[1][0] "3"; *TEXT w4.[1][0] "4"; *TEXT w5.[1][0] "5"; *TEXT "Encode2c"; .ENDS Encode2c_S .SUBCKT DS_Latch_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 23 24 Mtn0 18 17 1 24 TN W=2.00U L=0.80U Mtp4 6 19 20 23 TP W=2.00U L=0.80U Mtn4 20 2 18 24 TN W=2.00U L=0.80U Mtp0 7 13 19 23 TP W=2.00U L=0.80U Mtp5 19 2 21 23 TP W=2.00U L=0.80U Mtn5 21 13 4 24 TN W=2.00U L=0.80U Mtn6 3 18 5 24 TN W=2.00U L=0.80U Mtp6 8 14 3 23 TP W=1.20U L=0.80U Mtp1 9 13 17 23 TP W=4.00U L=0.80U Mtn1 17 13 10 24 TN W=2.00U L=0.80U Mtp2 11 15 16 23 TP W=4.00U L=0.80U Mtn3 16 15 12 24 TN W=2.00U L=0.80U *.GND gnd5 1 *.IN DataStrobe 2 *.OUT DS_Latch_bar3 3 *.GND gnd0 4 *.GND gnd1 5 *.VDD vdd1 6 *.VDD vdd2 7 *.VDD vdd3 8 *.VDD vdd0 9 *.GND gnd2 10 *.VDD vdd4 11 *.GND gnd6 12 *.IN Reset_bar 13 *.GND gnd3 14 *.IN Phi 15 *.OUT Phi_Bar 16 *.Vnwell 23 0 5 *.Vbulk 22 0 0 *.Vpwell 24 0 0 *.Vbulk 22 0 5 *TEXT tn0 " "; *TEXT tp4 " "; *TEXT tn4 " "; *TEXT tp0 " "; *TEXT tp5 " "; *TEXT tn5 " "; *TEXT tn6 " "; *TEXT tp6 " "; *TEXT tp1 " "; *TEXT tn1 " "; *TEXT tp2 " "; *TEXT tn3 " "; *TEXT "DS_Latch"; *TEXT "Note: in layout, this cell contains three terminals not shown: *DS_delay, DS_Latch_Bar1, and DS_Latch_bar2. *They are shorted together to form an intra-cell wire. *The terminals Phi2 and Phi_out also formed a wire with Phi. *To reduce the number of icon terminals, these schematic *wires will be implemented one level of hierarchy up from *this cell. *Also, the unused Reset terminal has been left out of the schematic."; .ENDS DS_Latch_S .SUBCKT Dff_Pos_Res_S 1 2 3 4 5 6 7 8 9 10 17 18 Mtn0 11 8 3 18 TN W=4.00U L=0.80U Mtp0 12 7 11 17 TP W=3.20U L=0.80U Mtp1 4 8 12 17 TP W=3.20U L=0.80U Mtp2 5 12 13 17 TP W=3.20U L=0.80U Mtn1 14 11 2 18 TN W=2.00U L=0.80U Mtn2 13 7 14 18 TN W=2.00U L=0.80U Mtp3 6 13 9 17 TP W=3.20U L=0.80U Mtn3 9 10 1 18 TN W=1.20U L=4.80U *.GND gnd3 1 *.GND gnd4 2 *.GND gnd5 3 *.VDD vdd0 4 *.VDD vdd1 5 *.VDD vdd2 6 *.IN Phi 7 *.IN D_in 8 *.OUT D_bar 9 *.VDD vdd3 10 *.Vnwell 17 0 5 *.Vbulk 16 0 0 *.Vpwell 18 0 0 *.Vbulk 16 0 5 *TEXT tn0 " "; *TEXT tp0 " "; *TEXT tp1 " "; *TEXT tp2 " "; *TEXT tn1 " "; *TEXT tn2 " "; *TEXT tp3 " "; *TEXT tn3 " "; *TEXT "Dff_Pos_Res"; *TEXT "Note: the redundant terminal Phi2 has been removed *from this schematic. It was shorted to Phi."; .ENDS Dff_Pos_Res_S .SUBCKT Mux2to1_S 1 2 3 4 5 6 11 12 Mtp6 2 3 7 11 TP W=4.00U L=0.80U Mtn7 7 3 1 12 TN W=2.00U L=0.80U Mtp0 8 7 4 11 TP W=4.00U L=0.80U Mtn0 4 3 8 12 TN W=2.00U L=0.80U Mtp1 8 3 5 11 TP W=4.00U L=0.80U Mtn2 5 7 8 12 TN W=2.00U L=0.80U Mtn1 9 8 1 12 TN W=2.00U L=0.80U Mtn3 6 9 1 12 TN W=2.00U L=0.80U Mtp2 2 8 9 11 TP W=3.20U L=0.80U Mtp3 2 9 6 11 TP W=3.20U L=0.80U *.GND gnd2 1 *.VDD vdd5 2 *.IN Select 3 *.IN Neg 4 *.IN Pos 5 *.OUT Out_To_Hit_Dff 6 *.Vnwell 11 0 5 *.Vbulk 10 0 0 *.Vpwell 12 0 0 *.Vbulk 10 0 5 *TEXT tp6 " "; *TEXT tn7 " "; *TEXT " "; *TEXT " "; *TEXT tp0 " "; *TEXT tn0 " "; *TEXT tp1 " "; *TEXT tn2 " "; *TEXT "Mux2to1"; *TEXT tn1 ""; *TEXT tn3 ""; *TEXT tp2 ""; *TEXT tp3 ""; .ENDS Mux2to1_S .SUBCKT Dff_PosEdge_S 1 2 3 4 5 6 7 8 9 15 16 Mtn0 10 8 3 16 TN W=4.00U L=0.80U Mtp0 11 7 10 15 TP W=3.20U L=0.80U Mtp1 4 8 11 15 TP W=3.20U L=0.80U Mtp2 5 11 12 15 TP W=3.20U L=0.80U Mtn1 13 10 2 16 TN W=2.00U L=0.80U Mtn2 12 7 13 16 TN W=2.00U L=0.80U Mtp3 6 12 9 15 TP W=3.20U L=0.80U Mtn3 9 13 1 16 TN W=2.00U L=0.80U *.GND gnd3 1 *.GND gnd4 2 *.GND gnd5 3 *.VDD vdd0 4 *.VDD vdd1 5 *.VDD vdd2 6 *.IN DStrobe2 7 *.IN D_in 8 *.OUT D_bar 9 *.Vnwell 15 0 5 *.Vbulk 14 0 0 *.Vpwell 16 0 0 *.Vbulk 14 0 5 *TEXT tn0 " "; *TEXT tp0 " "; *TEXT tp1 " "; *TEXT tp2 " "; *TEXT tn1 " "; *TEXT tn2 " "; *TEXT tp3 " "; *TEXT tn3 " "; *TEXT "Dff_PosEdge"; .ENDS Dff_PosEdge_S .SUBCKT HIT_Driver_S 1 2 3 4 5 6 7 8 9 12 13 Mtp4 4 9 10 12 TP W=4.00U L=0.80U Mtn4 10 9 1 13 TN W=2.00U L=0.80U Mtp5 5 10 8 12 TP W=8.00U L=0.80U Mtn6 8 10 2 13 TN W=4.00U L=0.80U Mtp6 6 8 7 12 TP W=16.00U L=0.80U Mtn7 7 8 3 13 TN W=8.00U L=0.80U *.GND gnd0 1 *.GND gnd1 2 *.GND gnd2 3 *.VDD vdd3 4 *.VDD vdd4 5 *.VDD vdd5 6 *.OUT Hit_Out 7 *.OUT Reset_bar 8 *.IN DS_in 9 *.Vnwell 12 0 5 *.Vbulk 11 0 0 *.Vpwell 13 0 0 *.Vbulk 11 0 5 *TEXT tp4 " "; *TEXT tn4 " "; *TEXT tp5 " "; *TEXT tn6 " "; *TEXT tp6 " "; *TEXT tn7 " "; *TEXT " "; *TEXT "HIT_Driver"; .ENDS HIT_Driver_S .SUBCKT DS_Driver_S 1 2 3 4 5 6 7 8 9 10 15 16 Mtp4 4 8 11 15 TP W=3.20U L=0.80U Mtn4 11 8 1 16 TN W=2.00U L=0.80U Mtp5 5 11 12 15 TP W=12.80U L=0.80U Mtn6 12 11 2 16 TN W=8.00U L=0.80U Mtp6 6 13 7 15 TP W=51.20U L=0.80U Mtn7 7 13 3 16 TN W=40.00U L=0.80U Mtp0 10 12 13 15 TP W=25.60U L=0.80U Mtn1 13 12 9 16 TN W=16.00U L=0.80U *.GND gnd0 1 *.GND gnd1 2 *.GND gnd2 3 *.VDD vdd3 4 *.VDD vdd4 5 *.VDD vdd5 6 *.OUT DS_bar 7 *.OUT DS 7 *.IN DS_in 8 *.GND gnd3 9 *.VDD vdd6 10 *.Vnwell 15 0 5 *.Vbulk 14 0 0 *.Vpwell 16 0 0 *.Vbulk 14 0 5 *TEXT tp4 " "; *TEXT tn4 " "; *TEXT tp5 " "; *TEXT tn6 " "; *TEXT tp6 " "; *TEXT tn7 " "; *TEXT " "; *TEXT tp0 " "; *TEXT tn1 " "; *TEXT " "; *TEXT " "; *TEXT "DS_Driver"; .ENDS DS_Driver_S .SUBCKT Ctrllogic_S 1 2 3 4 5 6 7 8 9 10 104 105 XDS_Latch_S_i0 11 8 12 13 14 15 16 17 18 19 20 21 22 23 7 24 104 105 + DS_Latch_S XDff_Pos_Res_S_i0 25 26 27 28 29 30 24 10 31 32 104 105 Dff_Pos_Res_S XDff_Pos_Res_S_i1 33 34 35 36 37 38 7 10 39 40 104 105 Dff_Pos_Res_S XMux2to1_S_i0 41 42 1 31 39 43 104 105 Mux2to1_S XDff_PosEdge_S_i0 44 45 46 47 48 49 7 43 50 104 105 Dff_PosEdge_S XHIT_Driver_S_i0 51 52 53 54 55 56 9 22 50 104 105 HIT_Driver_S XDS_Driver_S_i0 57 58 59 60 61 62 10 12 63 64 104 105 DS_Driver_S XEncode2c_S_i0 1 2 3 4 5 6 105 Encode2c_S *.OUT Out0_5_6 1 *.OUT Out0_4_6 2 *.OUT Out0_3_6 3 *.OUT Out0_2_6 4 *.OUT Out0_1_6 5 *.OUT Out0_0_6 6 *.OUT MSB 1 *.IN Phi_0 7 *.IN DataStrobe_0 8 *.OUT Hit_Out_5 9 *.OUT DS_bar_7 10 *.GND DS_Latch_S_i0.gnd5 11 *.IN DS_Latch_S_i0.DataStrobe 8 *.OUT DS_Latch_S_i0.DS_Latch_bar3 12 *.GND DS_Latch_S_i0.gnd0 13 *.GND DS_Latch_S_i0.gnd1 14 *.VDD DS_Latch_S_i0.vdd1 15 *.VDD DS_Latch_S_i0.vdd2 16 *.VDD DS_Latch_S_i0.vdd3 17 *.VDD DS_Latch_S_i0.vdd0 18 *.GND DS_Latch_S_i0.gnd2 19 *.VDD DS_Latch_S_i0.vdd4 20 *.GND DS_Latch_S_i0.gnd6 21 *.IN DS_Latch_S_i0.Reset_bar 22 *.GND DS_Latch_S_i0.gnd3 23 *.IN DS_Latch_S_i0.Phi 7 *.OUT DS_Latch_S_i0.Phi_Bar 24 *.GND Dff_Pos_Res_S_i0.gnd3 25 *.GND Dff_Pos_Res_S_i0.gnd4 26 *.GND Dff_Pos_Res_S_i0.gnd5 27 *.VDD Dff_Pos_Res_S_i0.vdd0 28 *.VDD Dff_Pos_Res_S_i0.vdd1 29 *.VDD Dff_Pos_Res_S_i0.vdd2 30 *.IN Dff_Pos_Res_S_i0.Phi 24 *.IN Dff_Pos_Res_S_i0.D_in 10 *.OUT Dff_Pos_Res_S_i0.D_bar 31 *.VDD Dff_Pos_Res_S_i0.vdd3 32 *.GND Dff_Pos_Res_S_i1.gnd3 33 *.GND Dff_Pos_Res_S_i1.gnd4 34 *.GND Dff_Pos_Res_S_i1.gnd5 35 *.VDD Dff_Pos_Res_S_i1.vdd0 36 *.VDD Dff_Pos_Res_S_i1.vdd1 37 *.VDD Dff_Pos_Res_S_i1.vdd2 38 *.IN Dff_Pos_Res_S_i1.Phi 7 *.IN Dff_Pos_Res_S_i1.D_in 10 *.OUT Dff_Pos_Res_S_i1.D_bar 39 *.VDD Dff_Pos_Res_S_i1.vdd3 40 *.GND Mux2to1_S_i0.gnd2 41 *.VDD Mux2to1_S_i0.vdd5 42 *.IN Mux2to1_S_i0.Select 1 *.IN Mux2to1_S_i0.Neg 31 *.IN Mux2to1_S_i0.Pos 39 *.OUT Mux2to1_S_i0.Out_To_Hit_Dff 43 *.GND Dff_PosEdge_S_i0.gnd3 44 *.GND Dff_PosEdge_S_i0.gnd4 45 *.GND Dff_PosEdge_S_i0.gnd5 46 *.VDD Dff_PosEdge_S_i0.vdd0 47 *.VDD Dff_PosEdge_S_i0.vdd1 48 *.VDD Dff_PosEdge_S_i0.vdd2 49 *.IN Dff_PosEdge_S_i0.DStrobe2 7 *.IN Dff_PosEdge_S_i0.D_in 43 *.OUT Dff_PosEdge_S_i0.D_bar 50 *.GND HIT_Driver_S_i0.gnd0 51 *.GND HIT_Driver_S_i0.gnd1 52 *.GND HIT_Driver_S_i0.gnd2 53 *.VDD HIT_Driver_S_i0.vdd3 54 *.VDD HIT_Driver_S_i0.vdd4 55 *.VDD HIT_Driver_S_i0.vdd5 56 *.OUT HIT_Driver_S_i0.Hit_Out 9 *.OUT HIT_Driver_S_i0.Reset_bar 22 *.IN HIT_Driver_S_i0.DS_in 50 *.GND DS_Driver_S_i0.gnd0 57 *.GND DS_Driver_S_i0.gnd1 58 *.GND DS_Driver_S_i0.gnd2 59 *.VDD DS_Driver_S_i0.vdd3 60 *.VDD DS_Driver_S_i0.vdd4 61 *.VDD DS_Driver_S_i0.vdd5 62 *.OUT DS_Driver_S_i0.DS_bar 10 *.OUT DS_Driver_S_i0.DS 10 *.IN DS_Driver_S_i0.DS_in 12 *.GND DS_Driver_S_i0.gnd3 63 *.VDD DS_Driver_S_i0.vdd6 64 *.OUT Encode2c_S_i0.out0[5] 1 *.OUT Encode2c_S_i0.out0[4] 2 *.OUT Encode2c_S_i0.out0[3] 3 *.OUT Encode2c_S_i0.out0[2] 4 *.OUT Encode2c_S_i0.out0[1] 5 *.OUT Encode2c_S_i0.out0[0] 6 *.Vnwell 104 0 5 *.Vbulk 103 0 0 *.Vpwell 105 0 0 *.Vbulk 103 0 5 VGND822 11 0 0 VGND823 13 0 0 VGND824 14 0 0 VVDD760 15 0 5.00 VVDD761 16 0 5.00 VVDD762 17 0 5.00 VVDD763 18 0 5.00 VGND825 19 0 0 VVDD764 20 0 5.00 VGND826 21 0 0 VGND827 23 0 0 VGND828 25 0 0 VGND829 26 0 0 VGND830 27 0 0 VVDD765 28 0 5.00 VVDD766 29 0 5.00 VVDD767 30 0 5.00 VVDD768 32 0 5.00 VGND831 33 0 0 VGND832 34 0 0 VGND833 35 0 0 VVDD769 36 0 5.00 VVDD770 37 0 5.00 VVDD771 38 0 5.00 VVDD772 40 0 5.00 VGND834 41 0 0 VVDD773 42 0 5.00 VGND835 44 0 0 VGND836 45 0 0 VGND837 46 0 0 VVDD774 47 0 5.00 VVDD775 48 0 5.00 VVDD776 49 0 5.00 VGND838 51 0 0 VGND839 52 0 0 VGND840 53 0 0 VVDD777 54 0 5.00 VVDD778 55 0 5.00 VVDD779 56 0 5.00 VGND841 57 0 0 VGND842 58 0 0 VGND843 59 0 0 VVDD780 60 0 5.00 VVDD781 61 0 5.00 VVDD782 62 0 5.00 VGND844 63 0 0 VVDD783 64 0 5.00 *TEXT w7.[1][0] "5"; *TEXT w2.[1][0] "4"; *TEXT w3.[1][0] "3"; *TEXT w4.[1][0] "2"; *TEXT w5.[1][0] "1"; *TEXT w6.[1][0] "0"; *TEXT "Ctrllogic"; .ENDS Ctrllogic_S .SUBCKT Encode2b_tile_S 1 *.INOUT out0 1 *.INOUT out1 1 *TEXT "Encode2b_tile"; .ENDS Encode2b_tile_S .SUBCKT Encode2_tile_S 1 2 3 5 Mtp0 3 2 1 5 TP W=4.00U L=0.80U *.OUT out0 1 *.OUT out1 1 *.IN in0 2 *.VDD vdd0 3 *.Vnwell 5 0 5 *.Vbulk 4 0 0 *TEXT tp0 " "; *TEXT "Encode2_tile"; .ENDS Encode2_tile_S .SUBCKT enc2_cell0_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 + 23 24 25 26 27 28 29 30 31 32 33 67 XEncode2b_tile_S_i0 33 Encode2b_tile_S XEncode2_tile_S_i0 33 32 34 67 Encode2_tile_S XEncode2_tile_S_i1 33 31 35 67 Encode2_tile_S XEncode2b_tile_S_i1 33 Encode2b_tile_S XEncode2b_tile_S_i2 33 Encode2b_tile_S XEncode2_tile_S_i2 33 30 36 67 Encode2_tile_S XEncode2_tile_S_i3 33 29 37 67 Encode2_tile_S XEncode2b_tile_S_i4 33 Encode2b_tile_S XEncode2b_tile_S_i5 33 Encode2b_tile_S XEncode2_tile_S_i4 33 28 38 67 Encode2_tile_S XEncode2_tile_S_i5 33 27 39 67 Encode2_tile_S XEncode2b_tile_S_i6 33 Encode2b_tile_S XEncode2b_tile_S_i7 33 Encode2b_tile_S XEncode2_tile_S_i8 33 26 40 67 Encode2_tile_S XEncode2_tile_S_i9 33 25 41 67 Encode2_tile_S XEncode2b_tile_S_i10 33 Encode2b_tile_S XEncode2b_tile_S_i11 33 Encode2b_tile_S XEncode2_tile_S_i6 33 24 42 67 Encode2_tile_S XEncode2_tile_S_i7 33 23 43 67 Encode2_tile_S XEncode2b_tile_S_i8 33 Encode2b_tile_S XEncode2b_tile_S_i9 33 Encode2b_tile_S XEncode2_tile_S_i10 33 22 44 67 Encode2_tile_S XEncode2_tile_S_i11 33 21 45 67 Encode2_tile_S XEncode2b_tile_S_i12 33 Encode2b_tile_S XEncode2b_tile_S_i13 33 Encode2b_tile_S XEncode2_tile_S_i14 33 20 46 67 Encode2_tile_S XEncode2_tile_S_i15 33 19 47 67 Encode2_tile_S XEncode2b_tile_S_i16 33 Encode2b_tile_S XEncode2b_tile_S_i17 33 Encode2b_tile_S XEncode2_tile_S_i18 33 18 48 67 Encode2_tile_S XEncode2_tile_S_i19 33 17 49 67 Encode2_tile_S XEncode2b_tile_S_i20 33 Encode2b_tile_S XEncode2b_tile_S_i21 33 Encode2b_tile_S XEncode2_tile_S_i12 33 16 50 67 Encode2_tile_S XEncode2_tile_S_i13 33 15 51 67 Encode2_tile_S XEncode2b_tile_S_i14 33 Encode2b_tile_S XEncode2b_tile_S_i15 33 Encode2b_tile_S XEncode2_tile_S_i16 33 14 52 67 Encode2_tile_S XEncode2_tile_S_i17 33 13 53 67 Encode2_tile_S XEncode2b_tile_S_i18 33 Encode2b_tile_S XEncode2b_tile_S_i19 33 Encode2b_tile_S XEncode2_tile_S_i20 33 12 54 67 Encode2_tile_S XEncode2_tile_S_i21 33 11 55 67 Encode2_tile_S XEncode2b_tile_S_i22 33 Encode2b_tile_S XEncode2b_tile_S_i23 33 Encode2b_tile_S XEncode2_tile_S_i24 33 10 56 67 Encode2_tile_S XEncode2_tile_S_i25 33 9 57 67 Encode2_tile_S XEncode2b_tile_S_i26 33 Encode2b_tile_S XEncode2b_tile_S_i27 33 Encode2b_tile_S XEncode2_tile_S_i28 33 8 58 67 Encode2_tile_S XEncode2_tile_S_i29 33 7 59 67 Encode2_tile_S XEncode2b_tile_S_i30 33 Encode2b_tile_S XEncode2b_tile_S_i31 33 Encode2b_tile_S XEncode2_tile_S_i32 33 6 60 67 Encode2_tile_S XEncode2_tile_S_i33 33 5 61 67 Encode2_tile_S XEncode2b_tile_S_i34 33 Encode2b_tile_S XEncode2b_tile_S_i35 33 Encode2b_tile_S XEncode2_tile_S_i36 33 4 62 67 Encode2_tile_S XEncode2_tile_S_i37 33 3 63 67 Encode2_tile_S XEncode2b_tile_S_i38 33 Encode2b_tile_S XEncode2b_tile_S_i39 33 Encode2b_tile_S XEncode2_tile_S_i40 33 2 64 67 Encode2_tile_S XEncode2_tile_S_i41 33 1 65 67 Encode2_tile_S XEncode2b_tile_S_i42 33 Encode2b_tile_S *.IN in0_tran[31] 1 *.IN in0_tran[30] 2 *.IN in0_tran[29] 3 *.IN in0_tran[28] 4 *.IN in0_tran[27] 5 *.IN in0_tran[26] 6 *.IN in0_tran[25] 7 *.IN in0_tran[24] 8 *.IN in0_tran[23] 9 *.IN in0_tran[22] 10 *.IN in0_tran[21] 11 *.IN in0_tran[20] 12 *.IN in0_tran[19] 13 *.IN in0_tran[18] 14 *.IN in0_tran[17] 15 *.IN in0_tran[16] 16 *.IN in0_tran[15] 17 *.IN in0_tran[14] 18 *.IN in0_tran[13] 19 *.IN in0_tran[12] 20 *.IN in0_tran[11] 21 *.IN in0_tran[10] 22 *.IN in0_tran[9] 23 *.IN in0_tran[8] 24 *.IN in0_tran[7] 25 *.IN in0_tran[6] 26 *.IN in0_tran[5] 27 *.IN in0_tran[4] 28 *.IN in0_tran[3] 29 *.IN in0_tran[2] 30 *.IN in0_tran[1] 31 *.IN in0_tran[0] 32 *.OUT out0_wire0 33 *.OUT out1_wire31 33 *.INOUT Encode2b_tile_S_i0.out0 33 *.INOUT Encode2b_tile_S_i0.out1 33 *.OUT Encode2_tile_S_i0.out0 33 *.OUT Encode2_tile_S_i0.out1 33 *.IN Encode2_tile_S_i0.in0 32 *.VDD Encode2_tile_S_i0.vdd0 34 *.OUT Encode2_tile_S_i1.out0 33 *.OUT Encode2_tile_S_i1.out1 33 *.IN Encode2_tile_S_i1.in0 31 *.VDD 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Encode2_tile_S_i11.vdd0 45 *.INOUT Encode2b_tile_S_i12.out0 33 *.INOUT Encode2b_tile_S_i12.out1 33 *.INOUT Encode2b_tile_S_i13.out0 33 *.INOUT Encode2b_tile_S_i13.out1 33 *.OUT Encode2_tile_S_i14.out0 33 *.OUT Encode2_tile_S_i14.out1 33 *.IN Encode2_tile_S_i14.in0 20 *.VDD Encode2_tile_S_i14.vdd0 46 *.OUT Encode2_tile_S_i15.out0 33 *.OUT Encode2_tile_S_i15.out1 33 *.IN Encode2_tile_S_i15.in0 19 *.VDD Encode2_tile_S_i15.vdd0 47 *.INOUT Encode2b_tile_S_i16.out0 33 *.INOUT Encode2b_tile_S_i16.out1 33 *.INOUT Encode2b_tile_S_i17.out0 33 *.INOUT Encode2b_tile_S_i17.out1 33 *.OUT Encode2_tile_S_i18.out0 33 *.OUT Encode2_tile_S_i18.out1 33 *.IN Encode2_tile_S_i18.in0 18 *.VDD Encode2_tile_S_i18.vdd0 48 *.OUT Encode2_tile_S_i19.out0 33 *.OUT Encode2_tile_S_i19.out1 33 *.IN Encode2_tile_S_i19.in0 17 *.VDD Encode2_tile_S_i19.vdd0 49 *.INOUT Encode2b_tile_S_i20.out0 33 *.INOUT Encode2b_tile_S_i20.out1 33 *.INOUT Encode2b_tile_S_i21.out0 33 *.INOUT Encode2b_tile_S_i21.out1 33 *.OUT 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*.IN Encode2_tile_S_i21.in0 11 *.VDD Encode2_tile_S_i21.vdd0 55 *.INOUT Encode2b_tile_S_i22.out0 33 *.INOUT Encode2b_tile_S_i22.out1 33 *.INOUT Encode2b_tile_S_i23.out0 33 *.INOUT Encode2b_tile_S_i23.out1 33 *.OUT Encode2_tile_S_i24.out0 33 *.OUT Encode2_tile_S_i24.out1 33 *.IN Encode2_tile_S_i24.in0 10 *.VDD Encode2_tile_S_i24.vdd0 56 *.OUT Encode2_tile_S_i25.out0 33 *.OUT Encode2_tile_S_i25.out1 33 *.IN Encode2_tile_S_i25.in0 9 *.VDD Encode2_tile_S_i25.vdd0 57 *.INOUT Encode2b_tile_S_i26.out0 33 *.INOUT Encode2b_tile_S_i26.out1 33 *.INOUT Encode2b_tile_S_i27.out0 33 *.INOUT Encode2b_tile_S_i27.out1 33 *.OUT Encode2_tile_S_i28.out0 33 *.OUT Encode2_tile_S_i28.out1 33 *.IN Encode2_tile_S_i28.in0 8 *.VDD Encode2_tile_S_i28.vdd0 58 *.OUT Encode2_tile_S_i29.out0 33 *.OUT Encode2_tile_S_i29.out1 33 *.IN Encode2_tile_S_i29.in0 7 *.VDD Encode2_tile_S_i29.vdd0 59 *.INOUT Encode2b_tile_S_i30.out0 33 *.INOUT Encode2b_tile_S_i30.out1 33 *.INOUT Encode2b_tile_S_i31.out0 33 *.INOUT Encode2b_tile_S_i31.out1 33 *.OUT Encode2_tile_S_i32.out0 33 *.OUT Encode2_tile_S_i32.out1 33 *.IN Encode2_tile_S_i32.in0 6 *.VDD Encode2_tile_S_i32.vdd0 60 *.OUT Encode2_tile_S_i33.out0 33 *.OUT Encode2_tile_S_i33.out1 33 *.IN Encode2_tile_S_i33.in0 5 *.VDD Encode2_tile_S_i33.vdd0 61 *.INOUT Encode2b_tile_S_i34.out0 33 *.INOUT Encode2b_tile_S_i34.out1 33 *.INOUT Encode2b_tile_S_i35.out0 33 *.INOUT Encode2b_tile_S_i35.out1 33 *.OUT Encode2_tile_S_i36.out0 33 *.OUT Encode2_tile_S_i36.out1 33 *.IN Encode2_tile_S_i36.in0 4 *.VDD Encode2_tile_S_i36.vdd0 62 *.OUT Encode2_tile_S_i37.out0 33 *.OUT Encode2_tile_S_i37.out1 33 *.IN Encode2_tile_S_i37.in0 3 *.VDD Encode2_tile_S_i37.vdd0 63 *.INOUT Encode2b_tile_S_i38.out0 33 *.INOUT Encode2b_tile_S_i38.out1 33 *.INOUT Encode2b_tile_S_i39.out0 33 *.INOUT Encode2b_tile_S_i39.out1 33 *.OUT Encode2_tile_S_i40.out0 33 *.OUT Encode2_tile_S_i40.out1 33 *.IN Encode2_tile_S_i40.in0 2 *.VDD Encode2_tile_S_i40.vdd0 64 *.OUT Encode2_tile_S_i41.out0 33 *.OUT Encode2_tile_S_i41.out1 33 *.IN Encode2_tile_S_i41.in0 1 *.VDD Encode2_tile_S_i41.vdd0 65 *.INOUT Encode2b_tile_S_i42.out0 33 *.INOUT Encode2b_tile_S_i42.out1 33 *.Vnwell 67 0 5 *.Vbulk 66 0 0 VVDD784 34 0 5.00 VVDD785 35 0 5.00 VVDD786 36 0 5.00 VVDD787 37 0 5.00 VVDD788 38 0 5.00 VVDD789 39 0 5.00 VVDD790 40 0 5.00 VVDD791 41 0 5.00 VVDD792 42 0 5.00 VVDD793 43 0 5.00 VVDD794 44 0 5.00 VVDD795 45 0 5.00 VVDD796 46 0 5.00 VVDD797 47 0 5.00 VVDD798 48 0 5.00 VVDD799 49 0 5.00 VVDD800 50 0 5.00 VVDD801 51 0 5.00 VVDD802 52 0 5.00 VVDD803 53 0 5.00 VVDD804 54 0 5.00 VVDD805 55 0 5.00 VVDD806 56 0 5.00 VVDD807 57 0 5.00 VVDD808 58 0 5.00 VVDD809 59 0 5.00 VVDD810 60 0 5.00 VVDD811 61 0 5.00 VVDD812 62 0 5.00 VVDD813 63 0 5.00 VVDD814 64 0 5.00 VVDD815 65 0 5.00 *TEXT w0.[1][8] "0"; *TEXT w1.[1][8] "1"; *TEXT w2.[1][8] "2"; *TEXT w3.[1][8] "3"; *TEXT w4.[1][8] "4"; *TEXT w5.[1][8] "5"; *TEXT w6.[1][8] "6"; *TEXT w7.[1][8] "7"; *TEXT w8.[1][8] "8"; *TEXT w9.[1][8] "9"; *TEXT w10.[1][8] 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XEncode2b_tile_S_i4 33 Encode2b_tile_S XEncode2b_tile_S_i5 33 Encode2b_tile_S XEncode2_tile_S_i4 33 28 38 67 Encode2_tile_S XEncode2_tile_S_i5 33 27 39 67 Encode2_tile_S XEncode2_tile_S_i6 33 26 40 67 Encode2_tile_S XEncode2_tile_S_i7 33 25 41 67 Encode2_tile_S XEncode2b_tile_S_i8 33 Encode2b_tile_S XEncode2b_tile_S_i9 33 Encode2b_tile_S XEncode2b_tile_S_i10 33 Encode2b_tile_S XEncode2b_tile_S_i11 33 Encode2b_tile_S XEncode2_tile_S_i8 33 24 42 67 Encode2_tile_S XEncode2_tile_S_i9 33 23 43 67 Encode2_tile_S XEncode2_tile_S_i10 33 22 44 67 Encode2_tile_S XEncode2_tile_S_i11 33 21 45 67 Encode2_tile_S XEncode2b_tile_S_i12 33 Encode2b_tile_S XEncode2b_tile_S_i13 33 Encode2b_tile_S XEncode2b_tile_S_i14 33 Encode2b_tile_S XEncode2b_tile_S_i15 33 Encode2b_tile_S XEncode2_tile_S_i16 33 20 46 67 Encode2_tile_S XEncode2_tile_S_i17 33 19 47 67 Encode2_tile_S XEncode2_tile_S_i18 33 18 48 67 Encode2_tile_S XEncode2_tile_S_i19 33 17 49 67 Encode2_tile_S XEncode2b_tile_S_i20 33 Encode2b_tile_S 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XEncode2b_tile_S_i32 33 Encode2b_tile_S XEncode2b_tile_S_i33 33 Encode2b_tile_S XEncode2b_tile_S_i34 33 Encode2b_tile_S XEncode2b_tile_S_i35 33 Encode2b_tile_S XEncode2_tile_S_i36 33 4 62 67 Encode2_tile_S XEncode2_tile_S_i37 33 3 63 67 Encode2_tile_S XEncode2_tile_S_i38 33 2 64 67 Encode2_tile_S XEncode2_tile_S_i39 33 1 65 67 Encode2_tile_S XEncode2b_tile_S_i40 33 Encode2b_tile_S XEncode2b_tile_S_i41 33 Encode2b_tile_S *.IN in0_tran[31] 1 *.IN in0_tran[30] 2 *.IN in0_tran[29] 3 *.IN in0_tran[28] 4 *.IN in0_tran[27] 5 *.IN in0_tran[26] 6 *.IN in0_tran[25] 7 *.IN in0_tran[24] 8 *.IN in0_tran[23] 9 *.IN in0_tran[22] 10 *.IN in0_tran[21] 11 *.IN in0_tran[20] 12 *.IN in0_tran[19] 13 *.IN in0_tran[18] 14 *.IN in0_tran[17] 15 *.IN in0_tran[16] 16 *.IN in0_tran[15] 17 *.IN in0_tran[14] 18 *.IN in0_tran[13] 19 *.IN in0_tran[12] 20 *.IN in0_tran[11] 21 *.IN in0_tran[10] 22 *.IN in0_tran[9] 23 *.IN in0_tran[8] 24 *.IN in0_tran[7] 25 *.IN in0_tran[6] 26 *.IN in0_tran[5] 27 *.IN in0_tran[4] 28 *.IN in0_tran[3] 29 *.IN in0_tran[2] 30 *.IN in0_tran[1] 31 *.IN in0_tran[0] 32 *.OUT out0_wire0 33 *.OUT out1_wire31 33 *.INOUT Encode2b_tile_S_i0.out0 33 *.INOUT Encode2b_tile_S_i0.out1 33 *.OUT Encode2_tile_S_i0.out0 33 *.OUT Encode2_tile_S_i0.out1 33 *.IN Encode2_tile_S_i0.in0 32 *.VDD Encode2_tile_S_i0.vdd0 34 *.INOUT Encode2b_tile_S_i1.out0 33 *.INOUT Encode2b_tile_S_i1.out1 33 *.OUT Encode2_tile_S_i1.out0 33 *.OUT Encode2_tile_S_i1.out1 33 *.IN Encode2_tile_S_i1.in0 31 *.VDD Encode2_tile_S_i1.vdd0 35 *.OUT Encode2_tile_S_i2.out0 33 *.OUT Encode2_tile_S_i2.out1 33 *.IN Encode2_tile_S_i2.in0 30 *.VDD Encode2_tile_S_i2.vdd0 36 *.OUT Encode2_tile_S_i3.out0 33 *.OUT Encode2_tile_S_i3.out1 33 *.IN Encode2_tile_S_i3.in0 29 *.VDD Encode2_tile_S_i3.vdd0 37 *.INOUT Encode2b_tile_S_i2.out0 33 *.INOUT Encode2b_tile_S_i2.out1 33 *.INOUT Encode2b_tile_S_i3.out0 33 *.INOUT Encode2b_tile_S_i3.out1 33 *.INOUT Encode2b_tile_S_i4.out0 33 *.INOUT Encode2b_tile_S_i4.out1 33 *.INOUT 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*.INOUT Encode2b_tile_S_i16.out0 33 *.INOUT Encode2b_tile_S_i16.out1 33 *.INOUT Encode2b_tile_S_i17.out0 33 *.INOUT Encode2b_tile_S_i17.out1 33 *.INOUT Encode2b_tile_S_i18.out0 33 *.INOUT Encode2b_tile_S_i18.out1 33 *.INOUT Encode2b_tile_S_i19.out0 33 *.INOUT Encode2b_tile_S_i19.out1 33 *.OUT Encode2_tile_S_i20.out0 33 *.OUT Encode2_tile_S_i20.out1 33 *.IN Encode2_tile_S_i20.in0 12 *.VDD Encode2_tile_S_i20.vdd0 54 *.OUT Encode2_tile_S_i21.out0 33 *.OUT Encode2_tile_S_i21.out1 33 *.IN Encode2_tile_S_i21.in0 11 *.VDD Encode2_tile_S_i21.vdd0 55 *.OUT Encode2_tile_S_i22.out0 33 *.OUT Encode2_tile_S_i22.out1 33 *.IN Encode2_tile_S_i22.in0 10 *.VDD Encode2_tile_S_i22.vdd0 56 *.OUT Encode2_tile_S_i23.out0 33 *.OUT Encode2_tile_S_i23.out1 33 *.IN Encode2_tile_S_i23.in0 9 *.VDD Encode2_tile_S_i23.vdd0 57 *.INOUT Encode2b_tile_S_i24.out0 33 *.INOUT Encode2b_tile_S_i24.out1 33 *.INOUT Encode2b_tile_S_i25.out0 33 *.INOUT Encode2b_tile_S_i25.out1 33 *.INOUT Encode2b_tile_S_i26.out0 33 *.INOUT Encode2b_tile_S_i26.out1 33 *.INOUT Encode2b_tile_S_i27.out0 33 *.INOUT Encode2b_tile_S_i27.out1 33 *.OUT Encode2_tile_S_i28.out0 33 *.OUT Encode2_tile_S_i28.out1 33 *.IN Encode2_tile_S_i28.in0 8 *.VDD Encode2_tile_S_i28.vdd0 58 *.OUT Encode2_tile_S_i29.out0 33 *.OUT Encode2_tile_S_i29.out1 33 *.IN Encode2_tile_S_i29.in0 7 *.VDD Encode2_tile_S_i29.vdd0 59 *.OUT Encode2_tile_S_i30.out0 33 *.OUT Encode2_tile_S_i30.out1 33 *.IN Encode2_tile_S_i30.in0 6 *.VDD Encode2_tile_S_i30.vdd0 60 *.OUT Encode2_tile_S_i31.out0 33 *.OUT Encode2_tile_S_i31.out1 33 *.IN Encode2_tile_S_i31.in0 5 *.VDD Encode2_tile_S_i31.vdd0 61 *.INOUT Encode2b_tile_S_i32.out0 33 *.INOUT Encode2b_tile_S_i32.out1 33 *.INOUT Encode2b_tile_S_i33.out0 33 *.INOUT Encode2b_tile_S_i33.out1 33 *.INOUT Encode2b_tile_S_i34.out0 33 *.INOUT Encode2b_tile_S_i34.out1 33 *.INOUT Encode2b_tile_S_i35.out0 33 *.INOUT Encode2b_tile_S_i35.out1 33 *.OUT Encode2_tile_S_i36.out0 33 *.OUT Encode2_tile_S_i36.out1 33 *.IN Encode2_tile_S_i36.in0 4 *.VDD Encode2_tile_S_i36.vdd0 62 *.OUT Encode2_tile_S_i37.out0 33 *.OUT Encode2_tile_S_i37.out1 33 *.IN Encode2_tile_S_i37.in0 3 *.VDD Encode2_tile_S_i37.vdd0 63 *.OUT Encode2_tile_S_i38.out0 33 *.OUT Encode2_tile_S_i38.out1 33 *.IN Encode2_tile_S_i38.in0 2 *.VDD Encode2_tile_S_i38.vdd0 64 *.OUT Encode2_tile_S_i39.out0 33 *.OUT Encode2_tile_S_i39.out1 33 *.IN Encode2_tile_S_i39.in0 1 *.VDD Encode2_tile_S_i39.vdd0 65 *.INOUT Encode2b_tile_S_i40.out0 33 *.INOUT Encode2b_tile_S_i40.out1 33 *.INOUT Encode2b_tile_S_i41.out0 33 *.INOUT Encode2b_tile_S_i41.out1 33 *.Vnwell 67 0 5 *.Vbulk 66 0 0 VVDD816 34 0 5.00 VVDD817 35 0 5.00 VVDD818 36 0 5.00 VVDD819 37 0 5.00 VVDD820 38 0 5.00 VVDD821 39 0 5.00 VVDD822 40 0 5.00 VVDD823 41 0 5.00 VVDD824 42 0 5.00 VVDD825 43 0 5.00 VVDD826 44 0 5.00 VVDD827 45 0 5.00 VVDD828 46 0 5.00 VVDD829 47 0 5.00 VVDD830 48 0 5.00 VVDD831 49 0 5.00 VVDD832 50 0 5.00 VVDD833 51 0 5.00 VVDD834 52 0 5.00 VVDD835 53 0 5.00 VVDD836 54 0 5.00 VVDD837 55 0 5.00 VVDD838 56 0 5.00 VVDD839 57 0 5.00 VVDD840 58 0 5.00 VVDD841 59 0 5.00 VVDD842 60 0 5.00 VVDD843 61 0 5.00 VVDD844 62 0 5.00 VVDD845 63 0 5.00 VVDD846 64 0 5.00 VVDD847 65 0 5.00 *TEXT w0.[1][9] "0"; *TEXT w1.[1][9] "1"; *TEXT w2.[1][9] "2"; *TEXT w3.[1][9] "3"; *TEXT w4.[1][9] "4"; *TEXT w5.[1][9] "5"; *TEXT w6.[1][9] "6"; *TEXT w7.[1][9] "7"; *TEXT w8.[1][9] "8"; *TEXT w9.[1][9] "9"; *TEXT w10.[1][9] "10"; *TEXT w11.[1][9] "11"; *TEXT w12.[1][9] "12"; *TEXT w13.[1][9] "13"; *TEXT w14.[1][9] "14"; *TEXT w15.[1][9] "15"; *TEXT w16.[1][9] "16"; *TEXT w17.[1][9] "17"; *TEXT w18.[1][9] "18"; *TEXT w19.[1][9] "19"; *TEXT w20.[1][9] "20"; *TEXT w21.[1][9] "21"; *TEXT w22.[1][9] "22"; *TEXT w23.[1][9] "23"; *TEXT w24.[1][9] "24"; *TEXT w25.[1][9] "25"; *TEXT w26.[1][9] "26"; *TEXT w27.[1][9] "27"; *TEXT w28.[1][9] "28"; *TEXT w29.[1][9] "29"; *TEXT w30.[1][9] "30"; *TEXT w31.[1][9] "31"; *TEXT "enc2_cell1"; .ENDS enc2_cell1_S .SUBCKT enc2_cell2_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 + 23 24 25 26 27 28 29 30 31 32 33 67 XEncode2_tile_S_i0 33 32 34 67 Encode2_tile_S XEncode2_tile_S_i1 33 31 35 67 Encode2_tile_S XEncode2_tile_S_i2 33 30 36 67 Encode2_tile_S XEncode2_tile_S_i3 33 29 37 67 Encode2_tile_S XEncode2_tile_S_i4 33 28 38 67 Encode2_tile_S XEncode2_tile_S_i5 33 27 39 67 Encode2_tile_S XEncode2_tile_S_i6 33 26 40 67 Encode2_tile_S XEncode2_tile_S_i7 33 25 41 67 Encode2_tile_S XEncode2b_tile_S_i0 33 Encode2b_tile_S XEncode2b_tile_S_i1 33 Encode2b_tile_S XEncode2b_tile_S_i2 33 Encode2b_tile_S XEncode2b_tile_S_i3 33 Encode2b_tile_S XEncode2b_tile_S_i4 33 Encode2b_tile_S XEncode2b_tile_S_i5 33 Encode2b_tile_S XEncode2b_tile_S_i6 33 Encode2b_tile_S XEncode2b_tile_S_i7 33 Encode2b_tile_S XEncode2_tile_S_i8 33 24 42 67 Encode2_tile_S XEncode2_tile_S_i9 33 23 43 67 Encode2_tile_S XEncode2_tile_S_i10 33 22 44 67 Encode2_tile_S XEncode2_tile_S_i11 33 21 45 67 Encode2_tile_S XEncode2_tile_S_i12 33 20 46 67 Encode2_tile_S XEncode2_tile_S_i13 33 19 47 67 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Encode2_tile_S_i23.vdd0 57 *.OUT Encode2_tile_S_i24.out0 33 *.OUT Encode2_tile_S_i24.out1 33 *.IN Encode2_tile_S_i24.in0 8 *.VDD Encode2_tile_S_i24.vdd0 58 *.OUT Encode2_tile_S_i25.out0 33 *.OUT Encode2_tile_S_i25.out1 33 *.IN Encode2_tile_S_i25.in0 7 *.VDD Encode2_tile_S_i25.vdd0 59 *.OUT Encode2_tile_S_i26.out0 33 *.OUT Encode2_tile_S_i26.out1 33 *.IN Encode2_tile_S_i26.in0 6 *.VDD Encode2_tile_S_i26.vdd0 60 *.OUT Encode2_tile_S_i27.out0 33 *.OUT Encode2_tile_S_i27.out1 33 *.IN Encode2_tile_S_i27.in0 5 *.VDD Encode2_tile_S_i27.vdd0 61 *.OUT Encode2_tile_S_i28.out0 33 *.OUT Encode2_tile_S_i28.out1 33 *.IN Encode2_tile_S_i28.in0 4 *.VDD Encode2_tile_S_i28.vdd0 62 *.OUT Encode2_tile_S_i29.out0 33 *.OUT Encode2_tile_S_i29.out1 33 *.IN Encode2_tile_S_i29.in0 3 *.VDD Encode2_tile_S_i29.vdd0 63 *.OUT Encode2_tile_S_i30.out0 33 *.OUT Encode2_tile_S_i30.out1 33 *.IN Encode2_tile_S_i30.in0 2 *.VDD Encode2_tile_S_i30.vdd0 64 *.OUT Encode2_tile_S_i31.out0 33 *.OUT Encode2_tile_S_i31.out1 33 *.IN Encode2_tile_S_i31.in0 1 *.VDD Encode2_tile_S_i31.vdd0 65 *.Vnwell 67 0 5 *.Vbulk 66 0 0 VVDD944 34 0 5.00 VVDD945 35 0 5.00 VVDD946 36 0 5.00 VVDD947 37 0 5.00 VVDD948 38 0 5.00 VVDD949 39 0 5.00 VVDD950 40 0 5.00 VVDD951 41 0 5.00 VVDD952 42 0 5.00 VVDD953 43 0 5.00 VVDD954 44 0 5.00 VVDD955 45 0 5.00 VVDD956 46 0 5.00 VVDD957 47 0 5.00 VVDD958 48 0 5.00 VVDD959 49 0 5.00 VVDD960 50 0 5.00 VVDD961 51 0 5.00 VVDD962 52 0 5.00 VVDD963 53 0 5.00 VVDD964 54 0 5.00 VVDD965 55 0 5.00 VVDD966 56 0 5.00 VVDD967 57 0 5.00 VVDD968 58 0 5.00 VVDD969 59 0 5.00 VVDD970 60 0 5.00 VVDD971 61 0 5.00 VVDD972 62 0 5.00 VVDD973 63 0 5.00 VVDD974 64 0 5.00 VVDD975 65 0 5.00 *TEXT "enc2_cell5"; *TEXT w0.[1][7] "0"; *TEXT w1.[1][7] "1"; *TEXT w2.[1][7] "2"; *TEXT w3.[1][7] "3"; *TEXT w4.[1][7] "4"; *TEXT w5.[1][7] "5"; *TEXT w6.[1][7] "6"; *TEXT w7.[1][7] "7"; *TEXT w8.[1][7] "8"; *TEXT w9.[1][7] "9"; *TEXT w10.[1][7] "10"; *TEXT w11.[1][7] "11"; *TEXT w12.[1][7] "12"; *TEXT w13.[1][7] "13"; *TEXT w14.[1][7] "14"; *TEXT w15.[1][7] "15"; *TEXT w16.[1][7] "16"; *TEXT w17.[1][7] "17"; *TEXT w18.[1][7] "18"; *TEXT w19.[1][7] "19"; *TEXT w20.[1][7] "20"; *TEXT w21.[1][7] "21"; *TEXT w22.[1][7] "22"; *TEXT w23.[1][7] "23"; *TEXT w24.[1][7] "24"; *TEXT w25.[1][7] "25"; *TEXT w26.[1][7] "26"; *TEXT w27.[1][7] "27"; *TEXT w28.[1][7] "28"; *TEXT w29.[1][7] "29"; *TEXT w30.[1][7] "30"; *TEXT w31.[1][7] "31"; .ENDS enc2_cell5_S .SUBCKT tdc_Encode2_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 + 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 + 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 263 Xenc2_cell0_S_i0 2 3 6 7 10 11 14 15 18 19 22 23 26 27 30 31 34 35 38 39 42 43 + 46 47 50 51 54 55 58 59 62 63 69 263 enc2_cell0_S Xenc2_cell1_S_i0 3 4 5 6 11 12 13 14 19 20 21 22 27 28 29 30 35 36 37 38 43 44 + 45 46 51 52 53 54 59 60 61 62 68 263 enc2_cell1_S Xenc2_cell2_S_i0 5 6 7 8 9 10 11 12 21 22 23 24 25 26 27 28 37 38 39 40 41 42 + 43 44 53 54 55 56 57 58 59 60 67 263 enc2_cell2_S Xenc2_cell3_S_i0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 66 263 enc2_cell3_S Xenc2_cell4_S_i0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 + 38 39 40 41 42 43 44 45 46 47 48 65 263 enc2_cell4_S Xenc2_cell5_S_i0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 + 25 26 27 28 29 30 31 32 64 263 enc2_cell5_S *.IN in[62] 1 *.IN in[61] 2 *.IN in[60] 3 *.IN in[59] 4 *.IN in[58] 5 *.IN in[57] 6 *.IN in[56] 7 *.IN in[55] 8 *.IN in[54] 9 *.IN in[53] 10 *.IN in[52] 11 *.IN in[51] 12 *.IN in[50] 13 *.IN in[49] 14 *.IN in[48] 15 *.IN in[47] 16 *.IN in[46] 17 *.IN in[45] 18 *.IN in[44] 19 *.IN in[43] 20 *.IN in[42] 21 *.IN in[41] 22 *.IN in[40] 23 *.IN in[39] 24 *.IN in[38] 25 *.IN in[37] 26 *.IN in[36] 27 *.IN in[35] 28 *.IN in[34] 29 *.IN in[33] 30 *.IN in[32] 31 *.IN in[31] 32 *.IN in[30] 33 *.IN in[29] 34 *.IN in[28] 35 *.IN in[27] 36 *.IN in[26] 37 *.IN in[25] 38 *.IN in[24] 39 *.IN in[23] 40 *.IN in[22] 41 *.IN in[21] 42 *.IN in[20] 43 *.IN in[19] 44 *.IN in[18] 45 *.IN in[17] 46 *.IN in[16] 47 *.IN in[15] 48 *.IN in[14] 49 *.IN in[13] 50 *.IN in[12] 51 *.IN in[11] 52 *.IN in[10] 53 *.IN in[9] 54 *.IN in[8] 55 *.IN in[7] 56 *.IN in[6] 57 *.IN in[5] 58 *.IN in[4] 59 *.IN in[3] 60 *.IN in[2] 61 *.IN in[1] 62 *.IN in[0] 63 *.OUT out[5] 64 *.OUT out[4] 65 *.OUT out[3] 66 *.OUT out[2] 67 *.OUT out[1] 68 *.OUT out[0] 69 *.IN enc2_cell0_S_i0.in0_tran[31] 2 *.IN enc2_cell0_S_i0.in0_tran[30] 3 *.IN enc2_cell0_S_i0.in0_tran[29] 6 *.IN enc2_cell0_S_i0.in0_tran[28] 7 *.IN enc2_cell0_S_i0.in0_tran[27] 10 *.IN enc2_cell0_S_i0.in0_tran[26] 11 *.IN enc2_cell0_S_i0.in0_tran[25] 14 *.IN enc2_cell0_S_i0.in0_tran[24] 15 *.IN enc2_cell0_S_i0.in0_tran[23] 18 *.IN enc2_cell0_S_i0.in0_tran[22] 19 *.IN enc2_cell0_S_i0.in0_tran[21] 22 *.IN enc2_cell0_S_i0.in0_tran[20] 23 *.IN enc2_cell0_S_i0.in0_tran[19] 26 *.IN enc2_cell0_S_i0.in0_tran[18] 27 *.IN enc2_cell0_S_i0.in0_tran[17] 30 *.IN enc2_cell0_S_i0.in0_tran[16] 31 *.IN enc2_cell0_S_i0.in0_tran[15] 34 *.IN enc2_cell0_S_i0.in0_tran[14] 35 *.IN enc2_cell0_S_i0.in0_tran[13] 38 *.IN enc2_cell0_S_i0.in0_tran[12] 39 *.IN enc2_cell0_S_i0.in0_tran[11] 42 *.IN enc2_cell0_S_i0.in0_tran[10] 43 *.IN enc2_cell0_S_i0.in0_tran[9] 46 *.IN enc2_cell0_S_i0.in0_tran[8] 47 *.IN enc2_cell0_S_i0.in0_tran[7] 50 *.IN enc2_cell0_S_i0.in0_tran[6] 51 *.IN enc2_cell0_S_i0.in0_tran[5] 54 *.IN enc2_cell0_S_i0.in0_tran[4] 55 *.IN enc2_cell0_S_i0.in0_tran[3] 58 *.IN enc2_cell0_S_i0.in0_tran[2] 59 *.IN enc2_cell0_S_i0.in0_tran[1] 62 *.IN enc2_cell0_S_i0.in0_tran[0] 63 *.OUT enc2_cell0_S_i0.out0_wire0 69 *.OUT enc2_cell0_S_i0.out1_wire31 69 *.IN enc2_cell1_S_i0.in0_tran[31] 3 *.IN enc2_cell1_S_i0.in0_tran[30] 4 *.IN enc2_cell1_S_i0.in0_tran[29] 5 *.IN enc2_cell1_S_i0.in0_tran[28] 6 *.IN enc2_cell1_S_i0.in0_tran[27] 11 *.IN enc2_cell1_S_i0.in0_tran[26] 12 *.IN enc2_cell1_S_i0.in0_tran[25] 13 *.IN enc2_cell1_S_i0.in0_tran[24] 14 *.IN enc2_cell1_S_i0.in0_tran[23] 19 *.IN enc2_cell1_S_i0.in0_tran[22] 20 *.IN enc2_cell1_S_i0.in0_tran[21] 21 *.IN enc2_cell1_S_i0.in0_tran[20] 22 *.IN enc2_cell1_S_i0.in0_tran[19] 27 *.IN enc2_cell1_S_i0.in0_tran[18] 28 *.IN enc2_cell1_S_i0.in0_tran[17] 29 *.IN enc2_cell1_S_i0.in0_tran[16] 30 *.IN enc2_cell1_S_i0.in0_tran[15] 35 *.IN enc2_cell1_S_i0.in0_tran[14] 36 *.IN enc2_cell1_S_i0.in0_tran[13] 37 *.IN enc2_cell1_S_i0.in0_tran[12] 38 *.IN enc2_cell1_S_i0.in0_tran[11] 43 *.IN enc2_cell1_S_i0.in0_tran[10] 44 *.IN enc2_cell1_S_i0.in0_tran[9] 45 *.IN enc2_cell1_S_i0.in0_tran[8] 46 *.IN enc2_cell1_S_i0.in0_tran[7] 51 *.IN enc2_cell1_S_i0.in0_tran[6] 52 *.IN enc2_cell1_S_i0.in0_tran[5] 53 *.IN enc2_cell1_S_i0.in0_tran[4] 54 *.IN enc2_cell1_S_i0.in0_tran[3] 59 *.IN enc2_cell1_S_i0.in0_tran[2] 60 *.IN enc2_cell1_S_i0.in0_tran[1] 61 *.IN enc2_cell1_S_i0.in0_tran[0] 62 *.OUT enc2_cell1_S_i0.out0_wire0 68 *.OUT enc2_cell1_S_i0.out1_wire31 68 *.IN enc2_cell2_S_i0.in0_tran[31] 5 *.IN enc2_cell2_S_i0.in0_tran[30] 6 *.IN enc2_cell2_S_i0.in0_tran[29] 7 *.IN enc2_cell2_S_i0.in0_tran[28] 8 *.IN enc2_cell2_S_i0.in0_tran[27] 9 *.IN enc2_cell2_S_i0.in0_tran[26] 10 *.IN enc2_cell2_S_i0.in0_tran[25] 11 *.IN enc2_cell2_S_i0.in0_tran[24] 12 *.IN enc2_cell2_S_i0.in0_tran[23] 21 *.IN enc2_cell2_S_i0.in0_tran[22] 22 *.IN enc2_cell2_S_i0.in0_tran[21] 23 *.IN enc2_cell2_S_i0.in0_tran[20] 24 *.IN enc2_cell2_S_i0.in0_tran[19] 25 *.IN enc2_cell2_S_i0.in0_tran[18] 26 *.IN enc2_cell2_S_i0.in0_tran[17] 27 *.IN enc2_cell2_S_i0.in0_tran[16] 28 *.IN enc2_cell2_S_i0.in0_tran[15] 37 *.IN enc2_cell2_S_i0.in0_tran[14] 38 *.IN enc2_cell2_S_i0.in0_tran[13] 39 *.IN enc2_cell2_S_i0.in0_tran[12] 40 *.IN enc2_cell2_S_i0.in0_tran[11] 41 *.IN enc2_cell2_S_i0.in0_tran[10] 42 *.IN enc2_cell2_S_i0.in0_tran[9] 43 *.IN enc2_cell2_S_i0.in0_tran[8] 44 *.IN enc2_cell2_S_i0.in0_tran[7] 53 *.IN enc2_cell2_S_i0.in0_tran[6] 54 *.IN enc2_cell2_S_i0.in0_tran[5] 55 *.IN enc2_cell2_S_i0.in0_tran[4] 56 *.IN enc2_cell2_S_i0.in0_tran[3] 57 *.IN enc2_cell2_S_i0.in0_tran[2] 58 *.IN enc2_cell2_S_i0.in0_tran[1] 59 *.IN enc2_cell2_S_i0.in0_tran[0] 60 *.OUT enc2_cell2_S_i0.out0_wire0 67 *.OUT enc2_cell2_S_i0.out1_wire31 67 *.IN enc2_cell3_S_i0.in0_tran[31] 9 *.IN enc2_cell3_S_i0.in0_tran[30] 10 *.IN enc2_cell3_S_i0.in0_tran[29] 11 *.IN enc2_cell3_S_i0.in0_tran[28] 12 *.IN enc2_cell3_S_i0.in0_tran[27] 13 *.IN enc2_cell3_S_i0.in0_tran[26] 14 *.IN enc2_cell3_S_i0.in0_tran[25] 15 *.IN enc2_cell3_S_i0.in0_tran[24] 16 *.IN enc2_cell3_S_i0.in0_tran[23] 17 *.IN enc2_cell3_S_i0.in0_tran[22] 18 *.IN enc2_cell3_S_i0.in0_tran[21] 19 *.IN enc2_cell3_S_i0.in0_tran[20] 20 *.IN enc2_cell3_S_i0.in0_tran[19] 21 *.IN enc2_cell3_S_i0.in0_tran[18] 22 *.IN enc2_cell3_S_i0.in0_tran[17] 23 *.IN enc2_cell3_S_i0.in0_tran[16] 24 *.IN enc2_cell3_S_i0.in0_tran[15] 41 *.IN enc2_cell3_S_i0.in0_tran[14] 42 *.IN enc2_cell3_S_i0.in0_tran[13] 43 *.IN enc2_cell3_S_i0.in0_tran[12] 44 *.IN enc2_cell3_S_i0.in0_tran[11] 45 *.IN enc2_cell3_S_i0.in0_tran[10] 46 *.IN enc2_cell3_S_i0.in0_tran[9] 47 *.IN enc2_cell3_S_i0.in0_tran[8] 48 *.IN enc2_cell3_S_i0.in0_tran[7] 49 *.IN enc2_cell3_S_i0.in0_tran[6] 50 *.IN enc2_cell3_S_i0.in0_tran[5] 51 *.IN enc2_cell3_S_i0.in0_tran[4] 52 *.IN enc2_cell3_S_i0.in0_tran[3] 53 *.IN enc2_cell3_S_i0.in0_tran[2] 54 *.IN enc2_cell3_S_i0.in0_tran[1] 55 *.IN enc2_cell3_S_i0.in0_tran[0] 56 *.OUT enc2_cell3_S_i0.out0_wire0 66 *.OUT enc2_cell3_S_i0.out1_wire31 66 *.IN enc2_cell4_S_i0.in0_tran[31] 17 *.IN enc2_cell4_S_i0.in0_tran[30] 18 *.IN enc2_cell4_S_i0.in0_tran[29] 19 *.IN enc2_cell4_S_i0.in0_tran[28] 20 *.IN enc2_cell4_S_i0.in0_tran[27] 21 *.IN enc2_cell4_S_i0.in0_tran[26] 22 *.IN enc2_cell4_S_i0.in0_tran[25] 23 *.IN enc2_cell4_S_i0.in0_tran[24] 24 *.IN enc2_cell4_S_i0.in0_tran[23] 25 *.IN enc2_cell4_S_i0.in0_tran[22] 26 *.IN enc2_cell4_S_i0.in0_tran[21] 27 *.IN enc2_cell4_S_i0.in0_tran[20] 28 *.IN enc2_cell4_S_i0.in0_tran[19] 29 *.IN enc2_cell4_S_i0.in0_tran[18] 30 *.IN enc2_cell4_S_i0.in0_tran[17] 31 *.IN enc2_cell4_S_i0.in0_tran[16] 32 *.IN enc2_cell4_S_i0.in0_tran[15] 33 *.IN enc2_cell4_S_i0.in0_tran[14] 34 *.IN enc2_cell4_S_i0.in0_tran[13] 35 *.IN enc2_cell4_S_i0.in0_tran[12] 36 *.IN enc2_cell4_S_i0.in0_tran[11] 37 *.IN enc2_cell4_S_i0.in0_tran[10] 38 *.IN enc2_cell4_S_i0.in0_tran[9] 39 *.IN enc2_cell4_S_i0.in0_tran[8] 40 *.IN enc2_cell4_S_i0.in0_tran[7] 41 *.IN enc2_cell4_S_i0.in0_tran[6] 42 *.IN enc2_cell4_S_i0.in0_tran[5] 43 *.IN enc2_cell4_S_i0.in0_tran[4] 44 *.IN enc2_cell4_S_i0.in0_tran[3] 45 *.IN enc2_cell4_S_i0.in0_tran[2] 46 *.IN enc2_cell4_S_i0.in0_tran[1] 47 *.IN enc2_cell4_S_i0.in0_tran[0] 48 *.OUT enc2_cell4_S_i0.out0_wire0 65 *.OUT enc2_cell4_S_i0.out1_wire31 65 *.IN enc2_cell5_S_i0.in0_tran[31] 1 *.IN enc2_cell5_S_i0.in0_tran[30] 2 *.IN enc2_cell5_S_i0.in0_tran[29] 3 *.IN enc2_cell5_S_i0.in0_tran[28] 4 *.IN enc2_cell5_S_i0.in0_tran[27] 5 *.IN enc2_cell5_S_i0.in0_tran[26] 6 *.IN enc2_cell5_S_i0.in0_tran[25] 7 *.IN enc2_cell5_S_i0.in0_tran[24] 8 *.IN enc2_cell5_S_i0.in0_tran[23] 9 *.IN enc2_cell5_S_i0.in0_tran[22] 10 *.IN enc2_cell5_S_i0.in0_tran[21] 11 *.IN enc2_cell5_S_i0.in0_tran[20] 12 *.IN enc2_cell5_S_i0.in0_tran[19] 13 *.IN enc2_cell5_S_i0.in0_tran[18] 14 *.IN enc2_cell5_S_i0.in0_tran[17] 15 *.IN enc2_cell5_S_i0.in0_tran[16] 16 *.IN enc2_cell5_S_i0.in0_tran[15] 17 *.IN enc2_cell5_S_i0.in0_tran[14] 18 *.IN enc2_cell5_S_i0.in0_tran[13] 19 *.IN enc2_cell5_S_i0.in0_tran[12] 20 *.IN enc2_cell5_S_i0.in0_tran[11] 21 *.IN enc2_cell5_S_i0.in0_tran[10] 22 *.IN enc2_cell5_S_i0.in0_tran[9] 23 *.IN enc2_cell5_S_i0.in0_tran[8] 24 *.IN enc2_cell5_S_i0.in0_tran[7] 25 *.IN enc2_cell5_S_i0.in0_tran[6] 26 *.IN enc2_cell5_S_i0.in0_tran[5] 27 *.IN enc2_cell5_S_i0.in0_tran[4] 28 *.IN enc2_cell5_S_i0.in0_tran[3] 29 *.IN enc2_cell5_S_i0.in0_tran[2] 30 *.IN enc2_cell5_S_i0.in0_tran[1] 31 *.IN enc2_cell5_S_i0.in0_tran[0] 32 *.OUT enc2_cell5_S_i0.out0_wire0 64 *.OUT enc2_cell5_S_i0.out1_wire31 64 *.Vnwell 263 0 5 *.Vbulk 262 0 0 *TEXT w0.[1][0] "61,60,57,56,53,52,49,48,45,44,41,40,37, *36,33,32,29,28,25,24,21,20,17,16,13,12, *9,8,5,4,1,0"; *TEXT w1.[1][0] "60,59,58,57,52,51,50,49,44,43,42,41,36, *35,34,33,28,27,26,25,20,19,18,17,12,11, *10,9,4,3,2,1"; *TEXT w2.[1][0] "58,57,56,55,54,53,52,51,42,41,40,39,38, *37,36,35,26,25,24,23,22,21,20,19,10,9, *8,7,6,5,4,3"; *TEXT w3.[1][0] "54,53,52,51,50,49,48,47,46,45,44,43,42, *41,40,39,22,21,20,19,18,17,16,15,14,13, *12,11,10,9,8,7"; *TEXT w4.[1][0] "46,45,44,43,42,41,40,39,38,37,36,35,34, *33,32,31,30,29,28,27,26,25,24,23,22,21, *20,19,18,17,16,15"; *TEXT w5.[1][0] "62,61,60,59,58,57,56,55,54,53,52,51,50, *49,48,47,46,45,44,43,42,41,40,39,38,37, *36,35,34,33,32,31"; *TEXT w6.[1][0] "0"; *TEXT w7.[1][0] "1"; *TEXT w8.[1][0] "2"; *TEXT w9.[1][0] "3"; *TEXT w10.[1][0] "4"; *TEXT w11.[1][0] "5"; *TEXT "tdc_Encode2"; .ENDS tdc_Encode2_S .SUBCKT Channel_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 1688 + 1689 XEncLatch_S_i0 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 74 75 76 77 78 79 80 81 82 83 84 + 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 + 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 + 127 128 129 130 131 132 133 134 135 136 137 1688 1689 EncLatch_S XEncode1_S_i0 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 + 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 + 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 + 136 137 74 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 + 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 + 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 1688 1689 Encode1_S XOutLatch_S_i0 138 139 140 141 142 143 65 68 69 70 71 72 73 1688 1689 + OutLatch_S XCtrllogic_S_i0 138 139 140 141 142 143 67 66 65 144 1688 1689 Ctrllogic_S Xtdc_Encode2_S_i0 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 + 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 + 198 199 200 201 202 203 204 205 206 207 138 139 140 141 142 143 1688 + tdc_Encode2_S *.IN D_in_[63] 1 *.IN D_in_[62] 2 *.IN D_in_[61] 3 *.IN D_in_[60] 4 *.IN D_in_[59] 5 *.IN D_in_[58] 6 *.IN D_in_[57] 7 *.IN D_in_[56] 8 *.IN D_in_[55] 9 *.IN D_in_[54] 10 *.IN D_in_[53] 11 *.IN D_in_[52] 12 *.IN D_in_[51] 13 *.IN D_in_[50] 14 *.IN D_in_[49] 15 *.IN D_in_[48] 16 *.IN D_in_[47] 17 *.IN D_in_[46] 18 *.IN D_in_[45] 19 *.IN D_in_[44] 20 *.IN D_in_[43] 21 *.IN D_in_[42] 22 *.IN D_in_[41] 23 *.IN D_in_[40] 24 *.IN D_in_[39] 25 *.IN D_in_[38] 26 *.IN D_in_[37] 27 *.IN D_in_[36] 28 *.IN D_in_[35] 29 *.IN D_in_[34] 30 *.IN D_in_[33] 31 *.IN D_in_[32] 32 *.IN D_in_[31] 33 *.IN D_in_[30] 34 *.IN D_in_[29] 35 *.IN D_in_[28] 36 *.IN D_in_[27] 37 *.IN D_in_[26] 38 *.IN D_in_[25] 39 *.IN D_in_[24] 40 *.IN D_in_[23] 41 *.IN D_in_[22] 42 *.IN D_in_[21] 43 *.IN D_in_[20] 44 *.IN D_in_[19] 45 *.IN D_in_[18] 46 *.IN D_in_[17] 47 *.IN D_in_[16] 48 *.IN D_in_[15] 49 *.IN D_in_[14] 50 *.IN D_in_[13] 51 *.IN D_in_[12] 52 *.IN D_in_[11] 53 *.IN D_in_[10] 54 *.IN D_in_[9] 55 *.IN D_in_[8] 56 *.IN D_in_[7] 57 *.IN D_in_[6] 58 *.IN D_in_[5] 59 *.IN D_in_[4] 60 *.IN D_in_[3] 61 *.IN D_in_[2] 62 *.IN D_in_[1] 63 *.IN D_in_[0] 64 *.IN HIT_5 65 *.IN DataStrobe_0 66 *.IN Phi_0 67 *.OUT Bit_[5] 68 *.OUT Bit_[4] 69 *.OUT Bit_[3] 70 *.OUT Bit_[2] 71 *.OUT Bit_[1] 72 *.OUT Bit_[0] 73 *.IN EncLatch_S_i0.DataStrobe_0 144 *.IN EncLatch_S_i0.DataStrobe_63 144 *.IN EncLatch_S_i0.D_in_[63] 1 *.IN EncLatch_S_i0.D_in_[62] 2 *.IN EncLatch_S_i0.D_in_[61] 3 *.IN EncLatch_S_i0.D_in_[60] 4 *.IN EncLatch_S_i0.D_in_[59] 5 *.IN EncLatch_S_i0.D_in_[58] 6 *.IN EncLatch_S_i0.D_in_[57] 7 *.IN EncLatch_S_i0.D_in_[56] 8 *.IN EncLatch_S_i0.D_in_[55] 9 *.IN EncLatch_S_i0.D_in_[54] 10 *.IN EncLatch_S_i0.D_in_[53] 11 *.IN EncLatch_S_i0.D_in_[52] 12 *.IN EncLatch_S_i0.D_in_[51] 13 *.IN EncLatch_S_i0.D_in_[50] 14 *.IN EncLatch_S_i0.D_in_[49] 15 *.IN EncLatch_S_i0.D_in_[48] 16 *.IN EncLatch_S_i0.D_in_[47] 17 *.IN EncLatch_S_i0.D_in_[46] 18 *.IN EncLatch_S_i0.D_in_[45] 19 *.IN EncLatch_S_i0.D_in_[44] 20 *.IN EncLatch_S_i0.D_in_[43] 21 *.IN EncLatch_S_i0.D_in_[42] 22 *.IN EncLatch_S_i0.D_in_[41] 23 *.IN EncLatch_S_i0.D_in_[40] 24 *.IN EncLatch_S_i0.D_in_[39] 25 *.IN EncLatch_S_i0.D_in_[38] 26 *.IN EncLatch_S_i0.D_in_[37] 27 *.IN EncLatch_S_i0.D_in_[36] 28 *.IN EncLatch_S_i0.D_in_[35] 29 *.IN EncLatch_S_i0.D_in_[34] 30 *.IN EncLatch_S_i0.D_in_[33] 31 *.IN EncLatch_S_i0.D_in_[32] 32 *.IN EncLatch_S_i0.D_in_[31] 33 *.IN EncLatch_S_i0.D_in_[30] 34 *.IN EncLatch_S_i0.D_in_[29] 35 *.IN EncLatch_S_i0.D_in_[28] 36 *.IN EncLatch_S_i0.D_in_[27] 37 *.IN EncLatch_S_i0.D_in_[26] 38 *.IN EncLatch_S_i0.D_in_[25] 39 *.IN EncLatch_S_i0.D_in_[24] 40 *.IN EncLatch_S_i0.D_in_[23] 41 *.IN EncLatch_S_i0.D_in_[22] 42 *.IN EncLatch_S_i0.D_in_[21] 43 *.IN EncLatch_S_i0.D_in_[20] 44 *.IN EncLatch_S_i0.D_in_[19] 45 *.IN EncLatch_S_i0.D_in_[18] 46 *.IN EncLatch_S_i0.D_in_[17] 47 *.IN EncLatch_S_i0.D_in_[16] 48 *.IN EncLatch_S_i0.D_in_[15] 49 *.IN EncLatch_S_i0.D_in_[14] 50 *.IN EncLatch_S_i0.D_in_[13] 51 *.IN EncLatch_S_i0.D_in_[12] 52 *.IN EncLatch_S_i0.D_in_[11] 53 *.IN EncLatch_S_i0.D_in_[10] 54 *.IN EncLatch_S_i0.D_in_[9] 55 *.IN EncLatch_S_i0.D_in_[8] 56 *.IN EncLatch_S_i0.D_in_[7] 57 *.IN EncLatch_S_i0.D_in_[6] 58 *.IN EncLatch_S_i0.D_in_[5] 59 *.IN EncLatch_S_i0.D_in_[4] 60 *.IN EncLatch_S_i0.D_in_[3] 61 *.IN EncLatch_S_i0.D_in_[2] 62 *.IN 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EncLatch_S_i0.D_bar_[36] 101 *.OUT EncLatch_S_i0.D_bar_[35] 102 *.OUT EncLatch_S_i0.D_bar_[34] 103 *.OUT EncLatch_S_i0.D_bar_[33] 104 *.OUT EncLatch_S_i0.D_bar_[32] 105 *.OUT EncLatch_S_i0.D_bar_[31] 106 *.OUT EncLatch_S_i0.D_bar_[30] 107 *.OUT EncLatch_S_i0.D_bar_[29] 108 *.OUT EncLatch_S_i0.D_bar_[28] 109 *.OUT EncLatch_S_i0.D_bar_[27] 110 *.OUT EncLatch_S_i0.D_bar_[26] 111 *.OUT EncLatch_S_i0.D_bar_[25] 112 *.OUT EncLatch_S_i0.D_bar_[24] 113 *.OUT EncLatch_S_i0.D_bar_[23] 114 *.OUT EncLatch_S_i0.D_bar_[22] 115 *.OUT EncLatch_S_i0.D_bar_[21] 116 *.OUT EncLatch_S_i0.D_bar_[20] 117 *.OUT EncLatch_S_i0.D_bar_[19] 118 *.OUT EncLatch_S_i0.D_bar_[18] 119 *.OUT EncLatch_S_i0.D_bar_[17] 120 *.OUT EncLatch_S_i0.D_bar_[16] 121 *.OUT EncLatch_S_i0.D_bar_[15] 122 *.OUT EncLatch_S_i0.D_bar_[14] 123 *.OUT EncLatch_S_i0.D_bar_[13] 124 *.OUT EncLatch_S_i0.D_bar_[12] 125 *.OUT EncLatch_S_i0.D_bar_[11] 126 *.OUT EncLatch_S_i0.D_bar_[10] 127 *.OUT EncLatch_S_i0.D_bar_[9] 128 *.OUT EncLatch_S_i0.D_bar_[8] 129 *.OUT EncLatch_S_i0.D_bar_[7] 130 *.OUT EncLatch_S_i0.D_bar_[6] 131 *.OUT EncLatch_S_i0.D_bar_[5] 132 *.OUT EncLatch_S_i0.D_bar_[4] 133 *.OUT EncLatch_S_i0.D_bar_[3] 134 *.OUT EncLatch_S_i0.D_bar_[2] 135 *.OUT EncLatch_S_i0.D_bar_[1] 136 *.OUT EncLatch_S_i0.D_bar_[0] 137 *.IN Encode1_S_i0.DFF_to_Enc1_[62] 75 *.IN Encode1_S_i0.DFF_to_Enc1_[61] 76 *.IN Encode1_S_i0.DFF_to_Enc1_[60] 77 *.IN Encode1_S_i0.DFF_to_Enc1_[59] 78 *.IN Encode1_S_i0.DFF_to_Enc1_[58] 79 *.IN Encode1_S_i0.DFF_to_Enc1_[57] 80 *.IN Encode1_S_i0.DFF_to_Enc1_[56] 81 *.IN Encode1_S_i0.DFF_to_Enc1_[55] 82 *.IN Encode1_S_i0.DFF_to_Enc1_[54] 83 *.IN Encode1_S_i0.DFF_to_Enc1_[53] 84 *.IN Encode1_S_i0.DFF_to_Enc1_[52] 85 *.IN Encode1_S_i0.DFF_to_Enc1_[51] 86 *.IN Encode1_S_i0.DFF_to_Enc1_[50] 87 *.IN Encode1_S_i0.DFF_to_Enc1_[49] 88 *.IN Encode1_S_i0.DFF_to_Enc1_[48] 89 *.IN Encode1_S_i0.DFF_to_Enc1_[47] 90 *.IN Encode1_S_i0.DFF_to_Enc1_[46] 91 *.IN Encode1_S_i0.DFF_to_Enc1_[45] 92 *.IN Encode1_S_i0.DFF_to_Enc1_[44] 93 *.IN Encode1_S_i0.DFF_to_Enc1_[43] 94 *.IN Encode1_S_i0.DFF_to_Enc1_[42] 95 *.IN Encode1_S_i0.DFF_to_Enc1_[41] 96 *.IN Encode1_S_i0.DFF_to_Enc1_[40] 97 *.IN Encode1_S_i0.DFF_to_Enc1_[39] 98 *.IN Encode1_S_i0.DFF_to_Enc1_[38] 99 *.IN Encode1_S_i0.DFF_to_Enc1_[37] 100 *.IN Encode1_S_i0.DFF_to_Enc1_[36] 101 *.IN Encode1_S_i0.DFF_to_Enc1_[35] 102 *.IN Encode1_S_i0.DFF_to_Enc1_[34] 103 *.IN Encode1_S_i0.DFF_to_Enc1_[33] 104 *.IN Encode1_S_i0.DFF_to_Enc1_[32] 105 *.IN Encode1_S_i0.DFF_to_Enc1_[31] 106 *.IN Encode1_S_i0.DFF_to_Enc1_[30] 107 *.IN Encode1_S_i0.DFF_to_Enc1_[29] 108 *.IN Encode1_S_i0.DFF_to_Enc1_[28] 109 *.IN Encode1_S_i0.DFF_to_Enc1_[27] 110 *.IN Encode1_S_i0.DFF_to_Enc1_[26] 111 *.IN Encode1_S_i0.DFF_to_Enc1_[25] 112 *.IN Encode1_S_i0.DFF_to_Enc1_[24] 113 *.IN Encode1_S_i0.DFF_to_Enc1_[23] 114 *.IN Encode1_S_i0.DFF_to_Enc1_[22] 115 *.IN Encode1_S_i0.DFF_to_Enc1_[21] 116 *.IN Encode1_S_i0.DFF_to_Enc1_[20] 117 *.IN Encode1_S_i0.DFF_to_Enc1_[19] 118 *.IN Encode1_S_i0.DFF_to_Enc1_[18] 119 *.IN Encode1_S_i0.DFF_to_Enc1_[17] 120 *.IN Encode1_S_i0.DFF_to_Enc1_[16] 121 *.IN Encode1_S_i0.DFF_to_Enc1_[15] 122 *.IN Encode1_S_i0.DFF_to_Enc1_[14] 123 *.IN Encode1_S_i0.DFF_to_Enc1_[13] 124 *.IN Encode1_S_i0.DFF_to_Enc1_[12] 125 *.IN Encode1_S_i0.DFF_to_Enc1_[11] 126 *.IN Encode1_S_i0.DFF_to_Enc1_[10] 127 *.IN Encode1_S_i0.DFF_to_Enc1_[9] 128 *.IN Encode1_S_i0.DFF_to_Enc1_[8] 129 *.IN Encode1_S_i0.DFF_to_Enc1_[7] 130 *.IN Encode1_S_i0.DFF_to_Enc1_[6] 131 *.IN Encode1_S_i0.DFF_to_Enc1_[5] 132 *.IN Encode1_S_i0.DFF_to_Enc1_[4] 133 *.IN Encode1_S_i0.DFF_to_Enc1_[3] 134 *.IN Encode1_S_i0.DFF_to_Enc1_[2] 135 *.IN Encode1_S_i0.DFF_to_Enc1_[1] 136 *.IN Encode1_S_i0.DFF_to_Enc1_[0] 137 *.IN Encode1_S_i0.Dff_to_Enc1inv_[62] 74 *.IN Encode1_S_i0.Dff_to_Enc1inv_[61] 75 *.IN Encode1_S_i0.Dff_to_Enc1inv_[60] 76 *.IN Encode1_S_i0.Dff_to_Enc1inv_[59] 77 *.IN Encode1_S_i0.Dff_to_Enc1inv_[58] 78 *.IN Encode1_S_i0.Dff_to_Enc1inv_[57] 79 *.IN Encode1_S_i0.Dff_to_Enc1inv_[56] 80 *.IN Encode1_S_i0.Dff_to_Enc1inv_[55] 81 *.IN Encode1_S_i0.Dff_to_Enc1inv_[54] 82 *.IN Encode1_S_i0.Dff_to_Enc1inv_[53] 83 *.IN Encode1_S_i0.Dff_to_Enc1inv_[52] 84 *.IN Encode1_S_i0.Dff_to_Enc1inv_[51] 85 *.IN Encode1_S_i0.Dff_to_Enc1inv_[50] 86 *.IN Encode1_S_i0.Dff_to_Enc1inv_[49] 87 *.IN Encode1_S_i0.Dff_to_Enc1inv_[48] 88 *.IN Encode1_S_i0.Dff_to_Enc1inv_[47] 89 *.IN Encode1_S_i0.Dff_to_Enc1inv_[46] 90 *.IN Encode1_S_i0.Dff_to_Enc1inv_[45] 91 *.IN Encode1_S_i0.Dff_to_Enc1inv_[44] 92 *.IN Encode1_S_i0.Dff_to_Enc1inv_[43] 93 *.IN Encode1_S_i0.Dff_to_Enc1inv_[42] 94 *.IN Encode1_S_i0.Dff_to_Enc1inv_[41] 95 *.IN Encode1_S_i0.Dff_to_Enc1inv_[40] 96 *.IN Encode1_S_i0.Dff_to_Enc1inv_[39] 97 *.IN Encode1_S_i0.Dff_to_Enc1inv_[38] 98 *.IN Encode1_S_i0.Dff_to_Enc1inv_[37] 99 *.IN Encode1_S_i0.Dff_to_Enc1inv_[36] 100 *.IN Encode1_S_i0.Dff_to_Enc1inv_[35] 101 *.IN Encode1_S_i0.Dff_to_Enc1inv_[34] 102 *.IN Encode1_S_i0.Dff_to_Enc1inv_[33] 103 *.IN Encode1_S_i0.Dff_to_Enc1inv_[32] 104 *.IN Encode1_S_i0.Dff_to_Enc1inv_[31] 105 *.IN Encode1_S_i0.Dff_to_Enc1inv_[30] 106 *.IN Encode1_S_i0.Dff_to_Enc1inv_[29] 107 *.IN Encode1_S_i0.Dff_to_Enc1inv_[28] 108 *.IN Encode1_S_i0.Dff_to_Enc1inv_[27] 109 *.IN Encode1_S_i0.Dff_to_Enc1inv_[26] 110 *.IN Encode1_S_i0.Dff_to_Enc1inv_[25] 111 *.IN Encode1_S_i0.Dff_to_Enc1inv_[24] 112 *.IN Encode1_S_i0.Dff_to_Enc1inv_[23] 113 *.IN Encode1_S_i0.Dff_to_Enc1inv_[22] 114 *.IN Encode1_S_i0.Dff_to_Enc1inv_[21] 115 *.IN Encode1_S_i0.Dff_to_Enc1inv_[20] 116 *.IN Encode1_S_i0.Dff_to_Enc1inv_[19] 117 *.IN Encode1_S_i0.Dff_to_Enc1inv_[18] 118 *.IN Encode1_S_i0.Dff_to_Enc1inv_[17] 119 *.IN Encode1_S_i0.Dff_to_Enc1inv_[16] 120 *.IN Encode1_S_i0.Dff_to_Enc1inv_[15] 121 *.IN Encode1_S_i0.Dff_to_Enc1inv_[14] 122 *.IN Encode1_S_i0.Dff_to_Enc1inv_[13] 123 *.IN Encode1_S_i0.Dff_to_Enc1inv_[12] 124 *.IN Encode1_S_i0.Dff_to_Enc1inv_[11] 125 *.IN Encode1_S_i0.Dff_to_Enc1inv_[10] 126 *.IN Encode1_S_i0.Dff_to_Enc1inv_[9] 127 *.IN Encode1_S_i0.Dff_to_Enc1inv_[8] 128 *.IN Encode1_S_i0.Dff_to_Enc1inv_[7] 129 *.IN Encode1_S_i0.Dff_to_Enc1inv_[6] 130 *.IN Encode1_S_i0.Dff_to_Enc1inv_[5] 131 *.IN Encode1_S_i0.Dff_to_Enc1inv_[4] 132 *.IN Encode1_S_i0.Dff_to_Enc1inv_[3] 133 *.IN Encode1_S_i0.Dff_to_Enc1inv_[2] 134 *.IN Encode1_S_i0.Dff_to_Enc1inv_[1] 135 *.IN Encode1_S_i0.Dff_to_Enc1inv_[0] 136 *.OUT Encode1_S_i0.Enc1_to_Enc2_[62] 145 *.OUT Encode1_S_i0.Enc1_to_Enc2_[61] 146 *.OUT Encode1_S_i0.Enc1_to_Enc2_[60] 147 *.OUT Encode1_S_i0.Enc1_to_Enc2_[59] 148 *.OUT Encode1_S_i0.Enc1_to_Enc2_[58] 149 *.OUT Encode1_S_i0.Enc1_to_Enc2_[57] 150 *.OUT Encode1_S_i0.Enc1_to_Enc2_[56] 151 *.OUT Encode1_S_i0.Enc1_to_Enc2_[55] 152 *.OUT Encode1_S_i0.Enc1_to_Enc2_[54] 153 *.OUT Encode1_S_i0.Enc1_to_Enc2_[53] 154 *.OUT Encode1_S_i0.Enc1_to_Enc2_[52] 155 *.OUT Encode1_S_i0.Enc1_to_Enc2_[51] 156 *.OUT Encode1_S_i0.Enc1_to_Enc2_[50] 157 *.OUT Encode1_S_i0.Enc1_to_Enc2_[49] 158 *.OUT Encode1_S_i0.Enc1_to_Enc2_[48] 159 *.OUT Encode1_S_i0.Enc1_to_Enc2_[47] 160 *.OUT Encode1_S_i0.Enc1_to_Enc2_[46] 161 *.OUT Encode1_S_i0.Enc1_to_Enc2_[45] 162 *.OUT Encode1_S_i0.Enc1_to_Enc2_[44] 163 *.OUT Encode1_S_i0.Enc1_to_Enc2_[43] 164 *.OUT Encode1_S_i0.Enc1_to_Enc2_[42] 165 *.OUT Encode1_S_i0.Enc1_to_Enc2_[41] 166 *.OUT Encode1_S_i0.Enc1_to_Enc2_[40] 167 *.OUT Encode1_S_i0.Enc1_to_Enc2_[39] 168 *.OUT Encode1_S_i0.Enc1_to_Enc2_[38] 169 *.OUT Encode1_S_i0.Enc1_to_Enc2_[37] 170 *.OUT Encode1_S_i0.Enc1_to_Enc2_[36] 171 *.OUT Encode1_S_i0.Enc1_to_Enc2_[35] 172 *.OUT Encode1_S_i0.Enc1_to_Enc2_[34] 173 *.OUT Encode1_S_i0.Enc1_to_Enc2_[33] 174 *.OUT Encode1_S_i0.Enc1_to_Enc2_[32] 175 *.OUT Encode1_S_i0.Enc1_to_Enc2_[31] 176 *.OUT Encode1_S_i0.Enc1_to_Enc2_[30] 177 *.OUT Encode1_S_i0.Enc1_to_Enc2_[29] 178 *.OUT Encode1_S_i0.Enc1_to_Enc2_[28] 179 *.OUT Encode1_S_i0.Enc1_to_Enc2_[27] 180 *.OUT Encode1_S_i0.Enc1_to_Enc2_[26] 181 *.OUT Encode1_S_i0.Enc1_to_Enc2_[25] 182 *.OUT Encode1_S_i0.Enc1_to_Enc2_[24] 183 *.OUT Encode1_S_i0.Enc1_to_Enc2_[23] 184 *.OUT Encode1_S_i0.Enc1_to_Enc2_[22] 185 *.OUT Encode1_S_i0.Enc1_to_Enc2_[21] 186 *.OUT Encode1_S_i0.Enc1_to_Enc2_[20] 187 *.OUT Encode1_S_i0.Enc1_to_Enc2_[19] 188 *.OUT Encode1_S_i0.Enc1_to_Enc2_[18] 189 *.OUT Encode1_S_i0.Enc1_to_Enc2_[17] 190 *.OUT Encode1_S_i0.Enc1_to_Enc2_[16] 191 *.OUT Encode1_S_i0.Enc1_to_Enc2_[15] 192 *.OUT Encode1_S_i0.Enc1_to_Enc2_[14] 193 *.OUT Encode1_S_i0.Enc1_to_Enc2_[13] 194 *.OUT Encode1_S_i0.Enc1_to_Enc2_[12] 195 *.OUT Encode1_S_i0.Enc1_to_Enc2_[11] 196 *.OUT Encode1_S_i0.Enc1_to_Enc2_[10] 197 *.OUT Encode1_S_i0.Enc1_to_Enc2_[9] 198 *.OUT Encode1_S_i0.Enc1_to_Enc2_[8] 199 *.OUT Encode1_S_i0.Enc1_to_Enc2_[7] 200 *.OUT Encode1_S_i0.Enc1_to_Enc2_[6] 201 *.OUT Encode1_S_i0.Enc1_to_Enc2_[5] 202 *.OUT Encode1_S_i0.Enc1_to_Enc2_[4] 203 *.OUT Encode1_S_i0.Enc1_to_Enc2_[3] 204 *.OUT Encode1_S_i0.Enc1_to_Enc2_[2] 205 *.OUT Encode1_S_i0.Enc1_to_Enc2_[1] 206 *.OUT Encode1_S_i0.Enc1_to_Enc2_[0] 207 *.IN OutLatch_S_i0.D_in[5] 138 *.IN OutLatch_S_i0.D_in[4] 139 *.IN OutLatch_S_i0.D_in[3] 140 *.IN OutLatch_S_i0.D_in[2] 141 *.IN OutLatch_S_i0.D_in[1] 142 *.IN OutLatch_S_i0.D_in[0] 143 *.IN OutLatch_S_i0.HIT_5 65 *.OUT OutLatch_S_i0.Bit[5] 68 *.OUT OutLatch_S_i0.Bit[4] 69 *.OUT OutLatch_S_i0.Bit[3] 70 *.OUT OutLatch_S_i0.Bit[2] 71 *.OUT OutLatch_S_i0.Bit[1] 72 *.OUT OutLatch_S_i0.Bit[0] 73 *.OUT Ctrllogic_S_i0.Out0_5_6 138 *.OUT Ctrllogic_S_i0.Out0_4_6 139 *.OUT Ctrllogic_S_i0.Out0_3_6 140 *.OUT Ctrllogic_S_i0.Out0_2_6 141 *.OUT Ctrllogic_S_i0.Out0_1_6 142 *.OUT Ctrllogic_S_i0.Out0_0_6 143 *.OUT Ctrllogic_S_i0.MSB 138 *.IN Ctrllogic_S_i0.Phi_0 67 *.IN Ctrllogic_S_i0.DataStrobe_0 66 *.OUT Ctrllogic_S_i0.Hit_Out_5 65 *.OUT Ctrllogic_S_i0.DS_bar_7 144 *.IN tdc_Encode2_S_i0.in[62] 145 *.IN tdc_Encode2_S_i0.in[61] 146 *.IN tdc_Encode2_S_i0.in[60] 147 *.IN tdc_Encode2_S_i0.in[59] 148 *.IN tdc_Encode2_S_i0.in[58] 149 *.IN tdc_Encode2_S_i0.in[57] 150 *.IN tdc_Encode2_S_i0.in[56] 151 *.IN tdc_Encode2_S_i0.in[55] 152 *.IN tdc_Encode2_S_i0.in[54] 153 *.IN tdc_Encode2_S_i0.in[53] 154 *.IN tdc_Encode2_S_i0.in[52] 155 *.IN tdc_Encode2_S_i0.in[51] 156 *.IN tdc_Encode2_S_i0.in[50] 157 *.IN tdc_Encode2_S_i0.in[49] 158 *.IN tdc_Encode2_S_i0.in[48] 159 *.IN tdc_Encode2_S_i0.in[47] 160 *.IN tdc_Encode2_S_i0.in[46] 161 *.IN tdc_Encode2_S_i0.in[45] 162 *.IN tdc_Encode2_S_i0.in[44] 163 *.IN tdc_Encode2_S_i0.in[43] 164 *.IN tdc_Encode2_S_i0.in[42] 165 *.IN tdc_Encode2_S_i0.in[41] 166 *.IN tdc_Encode2_S_i0.in[40] 167 *.IN tdc_Encode2_S_i0.in[39] 168 *.IN tdc_Encode2_S_i0.in[38] 169 *.IN tdc_Encode2_S_i0.in[37] 170 *.IN tdc_Encode2_S_i0.in[36] 171 *.IN tdc_Encode2_S_i0.in[35] 172 *.IN tdc_Encode2_S_i0.in[34] 173 *.IN tdc_Encode2_S_i0.in[33] 174 *.IN tdc_Encode2_S_i0.in[32] 175 *.IN tdc_Encode2_S_i0.in[31] 176 *.IN tdc_Encode2_S_i0.in[30] 177 *.IN tdc_Encode2_S_i0.in[29] 178 *.IN tdc_Encode2_S_i0.in[28] 179 *.IN tdc_Encode2_S_i0.in[27] 180 *.IN tdc_Encode2_S_i0.in[26] 181 *.IN tdc_Encode2_S_i0.in[25] 182 *.IN tdc_Encode2_S_i0.in[24] 183 *.IN tdc_Encode2_S_i0.in[23] 184 *.IN tdc_Encode2_S_i0.in[22] 185 *.IN tdc_Encode2_S_i0.in[21] 186 *.IN tdc_Encode2_S_i0.in[20] 187 *.IN tdc_Encode2_S_i0.in[19] 188 *.IN tdc_Encode2_S_i0.in[18] 189 *.IN tdc_Encode2_S_i0.in[17] 190 *.IN tdc_Encode2_S_i0.in[16] 191 *.IN tdc_Encode2_S_i0.in[15] 192 *.IN tdc_Encode2_S_i0.in[14] 193 *.IN tdc_Encode2_S_i0.in[13] 194 *.IN tdc_Encode2_S_i0.in[12] 195 *.IN tdc_Encode2_S_i0.in[11] 196 *.IN tdc_Encode2_S_i0.in[10] 197 *.IN tdc_Encode2_S_i0.in[9] 198 *.IN tdc_Encode2_S_i0.in[8] 199 *.IN tdc_Encode2_S_i0.in[7] 200 *.IN tdc_Encode2_S_i0.in[6] 201 *.IN tdc_Encode2_S_i0.in[5] 202 *.IN tdc_Encode2_S_i0.in[4] 203 *.IN tdc_Encode2_S_i0.in[3] 204 *.IN tdc_Encode2_S_i0.in[2] 205 *.IN tdc_Encode2_S_i0.in[1] 206 *.IN tdc_Encode2_S_i0.in[0] 207 *.OUT tdc_Encode2_S_i0.out[5] 138 *.OUT tdc_Encode2_S_i0.out[4] 139 *.OUT tdc_Encode2_S_i0.out[3] 140 *.OUT tdc_Encode2_S_i0.out[2] 141 *.OUT tdc_Encode2_S_i0.out[1] 142 *.OUT tdc_Encode2_S_i0.out[0] 143 *.Vnwell 1688 0 5 *.Vbulk 1687 0 0 *.Vpwell 1689 0 0 *.Vbulk 1687 0 5 *TEXT D_in_[63] " "; *TEXT HIT_5 " "; *TEXT DataStrobe_0 " "; *TEXT Phi_0 " "; *TEXT Bit_[5] " "; *TEXT node0[63] " "; *TEXT w0.[1][3] "62:0"; *TEXT w1.[1][0] "63:1"; *TEXT node1[5] " "; *TEXT w2.[1][0] "0"; *TEXT w3.[1][0] "1"; *TEXT w4.[1][0] "2"; *TEXT w5.[1][0] "3"; *TEXT w6.[1][0] "4"; *TEXT w7.[1][0] "5"; *TEXT "Channel"; .ENDS Channel_S .SUBCKT ChannelR_S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 1688 + 1689 XEncLatch_S_i0 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 74 75 76 77 78 79 80 81 82 83 84 + 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 + 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 + 127 128 129 130 131 132 133 134 135 136 137 1688 1689 EncLatch_S XEncode1_S_i0 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 + 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 + 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 + 136 137 74 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 + 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 + 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 1688 1689 Encode1_S XOutLatch_S_i0 138 139 140 141 142 143 65 68 69 70 71 72 73 1688 1689 + OutLatch_S XCtrllogic_S_i0 138 139 140 141 142 143 67 66 65 144 1688 1689 Ctrllogic_S Xtdc_Encode2_S_i0 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 + 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 + 198 199 200 201 202 203 204 205 206 207 138 139 140 141 142 143 1688 + tdc_Encode2_S *.IN D_in_[63] 1 *.IN D_in_[62] 2 *.IN D_in_[61] 3 *.IN D_in_[60] 4 *.IN D_in_[59] 5 *.IN D_in_[58] 6 *.IN D_in_[57] 7 *.IN D_in_[56] 8 *.IN D_in_[55] 9 *.IN D_in_[54] 10 *.IN D_in_[53] 11 *.IN D_in_[52] 12 *.IN D_in_[51] 13 *.IN D_in_[50] 14 *.IN D_in_[49] 15 *.IN D_in_[48] 16 *.IN D_in_[47] 17 *.IN D_in_[46] 18 *.IN D_in_[45] 19 *.IN D_in_[44] 20 *.IN D_in_[43] 21 *.IN D_in_[42] 22 *.IN D_in_[41] 23 *.IN D_in_[40] 24 *.IN D_in_[39] 25 *.IN D_in_[38] 26 *.IN D_in_[37] 27 *.IN D_in_[36] 28 *.IN D_in_[35] 29 *.IN D_in_[34] 30 *.IN D_in_[33] 31 *.IN D_in_[32] 32 *.IN D_in_[31] 33 *.IN D_in_[30] 34 *.IN D_in_[29] 35 *.IN D_in_[28] 36 *.IN D_in_[27] 37 *.IN D_in_[26] 38 *.IN D_in_[25] 39 *.IN D_in_[24] 40 *.IN D_in_[23] 41 *.IN D_in_[22] 42 *.IN D_in_[21] 43 *.IN D_in_[20] 44 *.IN D_in_[19] 45 *.IN D_in_[18] 46 *.IN D_in_[17] 47 *.IN D_in_[16] 48 *.IN D_in_[15] 49 *.IN D_in_[14] 50 *.IN D_in_[13] 51 *.IN D_in_[12] 52 *.IN D_in_[11] 53 *.IN D_in_[10] 54 *.IN D_in_[9] 55 *.IN D_in_[8] 56 *.IN D_in_[7] 57 *.IN D_in_[6] 58 *.IN D_in_[5] 59 *.IN D_in_[4] 60 *.IN D_in_[3] 61 *.IN D_in_[2] 62 *.IN D_in_[1] 63 *.IN D_in_[0] 64 *.IN HIT_5 65 *.IN DataStrobe_0 66 *.IN Phi_0 67 *.OUT Bit_[5] 68 *.OUT Bit_[4] 69 *.OUT Bit_[3] 70 *.OUT Bit_[2] 71 *.OUT Bit_[1] 72 *.OUT Bit_[0] 73 *.IN EncLatch_S_i0.DataStrobe_0 144 *.IN EncLatch_S_i0.DataStrobe_63 144 *.IN EncLatch_S_i0.D_in_[63] 1 *.IN EncLatch_S_i0.D_in_[62] 2 *.IN EncLatch_S_i0.D_in_[61] 3 *.IN EncLatch_S_i0.D_in_[60] 4 *.IN EncLatch_S_i0.D_in_[59] 5 *.IN EncLatch_S_i0.D_in_[58] 6 *.IN EncLatch_S_i0.D_in_[57] 7 *.IN EncLatch_S_i0.D_in_[56] 8 *.IN EncLatch_S_i0.D_in_[55] 9 *.IN EncLatch_S_i0.D_in_[54] 10 *.IN EncLatch_S_i0.D_in_[53] 11 *.IN EncLatch_S_i0.D_in_[52] 12 *.IN EncLatch_S_i0.D_in_[51] 13 *.IN EncLatch_S_i0.D_in_[50] 14 *.IN EncLatch_S_i0.D_in_[49] 15 *.IN EncLatch_S_i0.D_in_[48] 16 *.IN EncLatch_S_i0.D_in_[47] 17 *.IN EncLatch_S_i0.D_in_[46] 18 *.IN EncLatch_S_i0.D_in_[45] 19 *.IN EncLatch_S_i0.D_in_[44] 20 *.IN EncLatch_S_i0.D_in_[43] 21 *.IN EncLatch_S_i0.D_in_[42] 22 *.IN EncLatch_S_i0.D_in_[41] 23 *.IN EncLatch_S_i0.D_in_[40] 24 *.IN EncLatch_S_i0.D_in_[39] 25 *.IN EncLatch_S_i0.D_in_[38] 26 *.IN EncLatch_S_i0.D_in_[37] 27 *.IN EncLatch_S_i0.D_in_[36] 28 *.IN EncLatch_S_i0.D_in_[35] 29 *.IN EncLatch_S_i0.D_in_[34] 30 *.IN EncLatch_S_i0.D_in_[33] 31 *.IN EncLatch_S_i0.D_in_[32] 32 *.IN EncLatch_S_i0.D_in_[31] 33 *.IN EncLatch_S_i0.D_in_[30] 34 *.IN EncLatch_S_i0.D_in_[29] 35 *.IN EncLatch_S_i0.D_in_[28] 36 *.IN EncLatch_S_i0.D_in_[27] 37 *.IN EncLatch_S_i0.D_in_[26] 38 *.IN EncLatch_S_i0.D_in_[25] 39 *.IN EncLatch_S_i0.D_in_[24] 40 *.IN EncLatch_S_i0.D_in_[23] 41 *.IN EncLatch_S_i0.D_in_[22] 42 *.IN EncLatch_S_i0.D_in_[21] 43 *.IN EncLatch_S_i0.D_in_[20] 44 *.IN EncLatch_S_i0.D_in_[19] 45 *.IN EncLatch_S_i0.D_in_[18] 46 *.IN EncLatch_S_i0.D_in_[17] 47 *.IN EncLatch_S_i0.D_in_[16] 48 *.IN EncLatch_S_i0.D_in_[15] 49 *.IN EncLatch_S_i0.D_in_[14] 50 *.IN EncLatch_S_i0.D_in_[13] 51 *.IN EncLatch_S_i0.D_in_[12] 52 *.IN EncLatch_S_i0.D_in_[11] 53 *.IN EncLatch_S_i0.D_in_[10] 54 *.IN EncLatch_S_i0.D_in_[9] 55 *.IN EncLatch_S_i0.D_in_[8] 56 *.IN EncLatch_S_i0.D_in_[7] 57 *.IN EncLatch_S_i0.D_in_[6] 58 *.IN EncLatch_S_i0.D_in_[5] 59 *.IN EncLatch_S_i0.D_in_[4] 60 *.IN EncLatch_S_i0.D_in_[3] 61 *.IN EncLatch_S_i0.D_in_[2] 62 *.IN EncLatch_S_i0.D_in_[1] 63 *.IN EncLatch_S_i0.D_in_[0] 64 *.OUT EncLatch_S_i0.D_bar_[63] 74 *.OUT EncLatch_S_i0.D_bar_[62] 75 *.OUT EncLatch_S_i0.D_bar_[61] 76 *.OUT EncLatch_S_i0.D_bar_[60] 77 *.OUT EncLatch_S_i0.D_bar_[59] 78 *.OUT EncLatch_S_i0.D_bar_[58] 79 *.OUT EncLatch_S_i0.D_bar_[57] 80 *.OUT EncLatch_S_i0.D_bar_[56] 81 *.OUT EncLatch_S_i0.D_bar_[55] 82 *.OUT EncLatch_S_i0.D_bar_[54] 83 *.OUT EncLatch_S_i0.D_bar_[53] 84 *.OUT EncLatch_S_i0.D_bar_[52] 85 *.OUT EncLatch_S_i0.D_bar_[51] 86 *.OUT EncLatch_S_i0.D_bar_[50] 87 *.OUT EncLatch_S_i0.D_bar_[49] 88 *.OUT EncLatch_S_i0.D_bar_[48] 89 *.OUT EncLatch_S_i0.D_bar_[47] 90 *.OUT EncLatch_S_i0.D_bar_[46] 91 *.OUT EncLatch_S_i0.D_bar_[45] 92 *.OUT EncLatch_S_i0.D_bar_[44] 93 *.OUT EncLatch_S_i0.D_bar_[43] 94 *.OUT EncLatch_S_i0.D_bar_[42] 95 *.OUT EncLatch_S_i0.D_bar_[41] 96 *.OUT EncLatch_S_i0.D_bar_[40] 97 *.OUT EncLatch_S_i0.D_bar_[39] 98 *.OUT EncLatch_S_i0.D_bar_[38] 99 *.OUT EncLatch_S_i0.D_bar_[37] 100 *.OUT EncLatch_S_i0.D_bar_[36] 101 *.OUT EncLatch_S_i0.D_bar_[35] 102 *.OUT EncLatch_S_i0.D_bar_[34] 103 *.OUT EncLatch_S_i0.D_bar_[33] 104 *.OUT EncLatch_S_i0.D_bar_[32] 105 *.OUT EncLatch_S_i0.D_bar_[31] 106 *.OUT EncLatch_S_i0.D_bar_[30] 107 *.OUT EncLatch_S_i0.D_bar_[29] 108 *.OUT EncLatch_S_i0.D_bar_[28] 109 *.OUT EncLatch_S_i0.D_bar_[27] 110 *.OUT EncLatch_S_i0.D_bar_[26] 111 *.OUT EncLatch_S_i0.D_bar_[25] 112 *.OUT EncLatch_S_i0.D_bar_[24] 113 *.OUT EncLatch_S_i0.D_bar_[23] 114 *.OUT EncLatch_S_i0.D_bar_[22] 115 *.OUT EncLatch_S_i0.D_bar_[21] 116 *.OUT EncLatch_S_i0.D_bar_[20] 117 *.OUT EncLatch_S_i0.D_bar_[19] 118 *.OUT EncLatch_S_i0.D_bar_[18] 119 *.OUT EncLatch_S_i0.D_bar_[17] 120 *.OUT EncLatch_S_i0.D_bar_[16] 121 *.OUT EncLatch_S_i0.D_bar_[15] 122 *.OUT EncLatch_S_i0.D_bar_[14] 123 *.OUT EncLatch_S_i0.D_bar_[13] 124 *.OUT EncLatch_S_i0.D_bar_[12] 125 *.OUT EncLatch_S_i0.D_bar_[11] 126 *.OUT EncLatch_S_i0.D_bar_[10] 127 *.OUT EncLatch_S_i0.D_bar_[9] 128 *.OUT EncLatch_S_i0.D_bar_[8] 129 *.OUT EncLatch_S_i0.D_bar_[7] 130 *.OUT EncLatch_S_i0.D_bar_[6] 131 *.OUT EncLatch_S_i0.D_bar_[5] 132 *.OUT EncLatch_S_i0.D_bar_[4] 133 *.OUT EncLatch_S_i0.D_bar_[3] 134 *.OUT EncLatch_S_i0.D_bar_[2] 135 *.OUT EncLatch_S_i0.D_bar_[1] 136 *.OUT EncLatch_S_i0.D_bar_[0] 137 *.IN Encode1_S_i0.DFF_to_Enc1_[62] 75 *.IN Encode1_S_i0.DFF_to_Enc1_[61] 76 *.IN Encode1_S_i0.DFF_to_Enc1_[60] 77 *.IN Encode1_S_i0.DFF_to_Enc1_[59] 78 *.IN Encode1_S_i0.DFF_to_Enc1_[58] 79 *.IN Encode1_S_i0.DFF_to_Enc1_[57] 80 *.IN Encode1_S_i0.DFF_to_Enc1_[56] 81 *.IN Encode1_S_i0.DFF_to_Enc1_[55] 82 *.IN Encode1_S_i0.DFF_to_Enc1_[54] 83 *.IN Encode1_S_i0.DFF_to_Enc1_[53] 84 *.IN Encode1_S_i0.DFF_to_Enc1_[52] 85 *.IN Encode1_S_i0.DFF_to_Enc1_[51] 86 *.IN Encode1_S_i0.DFF_to_Enc1_[50] 87 *.IN Encode1_S_i0.DFF_to_Enc1_[49] 88 *.IN Encode1_S_i0.DFF_to_Enc1_[48] 89 *.IN Encode1_S_i0.DFF_to_Enc1_[47] 90 *.IN Encode1_S_i0.DFF_to_Enc1_[46] 91 *.IN Encode1_S_i0.DFF_to_Enc1_[45] 92 *.IN Encode1_S_i0.DFF_to_Enc1_[44] 93 *.IN Encode1_S_i0.DFF_to_Enc1_[43] 94 *.IN Encode1_S_i0.DFF_to_Enc1_[42] 95 *.IN Encode1_S_i0.DFF_to_Enc1_[41] 96 *.IN Encode1_S_i0.DFF_to_Enc1_[40] 97 *.IN Encode1_S_i0.DFF_to_Enc1_[39] 98 *.IN Encode1_S_i0.DFF_to_Enc1_[38] 99 *.IN Encode1_S_i0.DFF_to_Enc1_[37] 100 *.IN Encode1_S_i0.DFF_to_Enc1_[36] 101 *.IN Encode1_S_i0.DFF_to_Enc1_[35] 102 *.IN Encode1_S_i0.DFF_to_Enc1_[34] 103 *.IN Encode1_S_i0.DFF_to_Enc1_[33] 104 *.IN Encode1_S_i0.DFF_to_Enc1_[32] 105 *.IN Encode1_S_i0.DFF_to_Enc1_[31] 106 *.IN Encode1_S_i0.DFF_to_Enc1_[30] 107 *.IN Encode1_S_i0.DFF_to_Enc1_[29] 108 *.IN Encode1_S_i0.DFF_to_Enc1_[28] 109 *.IN Encode1_S_i0.DFF_to_Enc1_[27] 110 *.IN Encode1_S_i0.DFF_to_Enc1_[26] 111 *.IN Encode1_S_i0.DFF_to_Enc1_[25] 112 *.IN Encode1_S_i0.DFF_to_Enc1_[24] 113 *.IN Encode1_S_i0.DFF_to_Enc1_[23] 114 *.IN Encode1_S_i0.DFF_to_Enc1_[22] 115 *.IN Encode1_S_i0.DFF_to_Enc1_[21] 116 *.IN Encode1_S_i0.DFF_to_Enc1_[20] 117 *.IN Encode1_S_i0.DFF_to_Enc1_[19] 118 *.IN Encode1_S_i0.DFF_to_Enc1_[18] 119 *.IN Encode1_S_i0.DFF_to_Enc1_[17] 120 *.IN Encode1_S_i0.DFF_to_Enc1_[16] 121 *.IN Encode1_S_i0.DFF_to_Enc1_[15] 122 *.IN Encode1_S_i0.DFF_to_Enc1_[14] 123 *.IN Encode1_S_i0.DFF_to_Enc1_[13] 124 *.IN Encode1_S_i0.DFF_to_Enc1_[12] 125 *.IN Encode1_S_i0.DFF_to_Enc1_[11] 126 *.IN Encode1_S_i0.DFF_to_Enc1_[10] 127 *.IN Encode1_S_i0.DFF_to_Enc1_[9] 128 *.IN Encode1_S_i0.DFF_to_Enc1_[8] 129 *.IN Encode1_S_i0.DFF_to_Enc1_[7] 130 *.IN Encode1_S_i0.DFF_to_Enc1_[6] 131 *.IN Encode1_S_i0.DFF_to_Enc1_[5] 132 *.IN Encode1_S_i0.DFF_to_Enc1_[4] 133 *.IN Encode1_S_i0.DFF_to_Enc1_[3] 134 *.IN Encode1_S_i0.DFF_to_Enc1_[2] 135 *.IN Encode1_S_i0.DFF_to_Enc1_[1] 136 *.IN Encode1_S_i0.DFF_to_Enc1_[0] 137 *.IN Encode1_S_i0.Dff_to_Enc1inv_[62] 74 *.IN Encode1_S_i0.Dff_to_Enc1inv_[61] 75 *.IN Encode1_S_i0.Dff_to_Enc1inv_[60] 76 *.IN Encode1_S_i0.Dff_to_Enc1inv_[59] 77 *.IN Encode1_S_i0.Dff_to_Enc1inv_[58] 78 *.IN Encode1_S_i0.Dff_to_Enc1inv_[57] 79 *.IN Encode1_S_i0.Dff_to_Enc1inv_[56] 80 *.IN Encode1_S_i0.Dff_to_Enc1inv_[55] 81 *.IN Encode1_S_i0.Dff_to_Enc1inv_[54] 82 *.IN Encode1_S_i0.Dff_to_Enc1inv_[53] 83 *.IN Encode1_S_i0.Dff_to_Enc1inv_[52] 84 *.IN Encode1_S_i0.Dff_to_Enc1inv_[51] 85 *.IN Encode1_S_i0.Dff_to_Enc1inv_[50] 86 *.IN Encode1_S_i0.Dff_to_Enc1inv_[49] 87 *.IN Encode1_S_i0.Dff_to_Enc1inv_[48] 88 *.IN Encode1_S_i0.Dff_to_Enc1inv_[47] 89 *.IN Encode1_S_i0.Dff_to_Enc1inv_[46] 90 *.IN Encode1_S_i0.Dff_to_Enc1inv_[45] 91 *.IN Encode1_S_i0.Dff_to_Enc1inv_[44] 92 *.IN Encode1_S_i0.Dff_to_Enc1inv_[43] 93 *.IN Encode1_S_i0.Dff_to_Enc1inv_[42] 94 *.IN Encode1_S_i0.Dff_to_Enc1inv_[41] 95 *.IN Encode1_S_i0.Dff_to_Enc1inv_[40] 96 *.IN Encode1_S_i0.Dff_to_Enc1inv_[39] 97 *.IN Encode1_S_i0.Dff_to_Enc1inv_[38] 98 *.IN Encode1_S_i0.Dff_to_Enc1inv_[37] 99 *.IN Encode1_S_i0.Dff_to_Enc1inv_[36] 100 *.IN Encode1_S_i0.Dff_to_Enc1inv_[35] 101 *.IN Encode1_S_i0.Dff_to_Enc1inv_[34] 102 *.IN Encode1_S_i0.Dff_to_Enc1inv_[33] 103 *.IN Encode1_S_i0.Dff_to_Enc1inv_[32] 104 *.IN Encode1_S_i0.Dff_to_Enc1inv_[31] 105 *.IN Encode1_S_i0.Dff_to_Enc1inv_[30] 106 *.IN Encode1_S_i0.Dff_to_Enc1inv_[29] 107 *.IN Encode1_S_i0.Dff_to_Enc1inv_[28] 108 *.IN Encode1_S_i0.Dff_to_Enc1inv_[27] 109 *.IN Encode1_S_i0.Dff_to_Enc1inv_[26] 110 *.IN Encode1_S_i0.Dff_to_Enc1inv_[25] 111 *.IN Encode1_S_i0.Dff_to_Enc1inv_[24] 112 *.IN Encode1_S_i0.Dff_to_Enc1inv_[23] 113 *.IN Encode1_S_i0.Dff_to_Enc1inv_[22] 114 *.IN Encode1_S_i0.Dff_to_Enc1inv_[21] 115 *.IN Encode1_S_i0.Dff_to_Enc1inv_[20] 116 *.IN Encode1_S_i0.Dff_to_Enc1inv_[19] 117 *.IN Encode1_S_i0.Dff_to_Enc1inv_[18] 118 *.IN Encode1_S_i0.Dff_to_Enc1inv_[17] 119 *.IN Encode1_S_i0.Dff_to_Enc1inv_[16] 120 *.IN Encode1_S_i0.Dff_to_Enc1inv_[15] 121 *.IN Encode1_S_i0.Dff_to_Enc1inv_[14] 122 *.IN Encode1_S_i0.Dff_to_Enc1inv_[13] 123 *.IN Encode1_S_i0.Dff_to_Enc1inv_[12] 124 *.IN Encode1_S_i0.Dff_to_Enc1inv_[11] 125 *.IN Encode1_S_i0.Dff_to_Enc1inv_[10] 126 *.IN Encode1_S_i0.Dff_to_Enc1inv_[9] 127 *.IN Encode1_S_i0.Dff_to_Enc1inv_[8] 128 *.IN Encode1_S_i0.Dff_to_Enc1inv_[7] 129 *.IN Encode1_S_i0.Dff_to_Enc1inv_[6] 130 *.IN Encode1_S_i0.Dff_to_Enc1inv_[5] 131 *.IN Encode1_S_i0.Dff_to_Enc1inv_[4] 132 *.IN Encode1_S_i0.Dff_to_Enc1inv_[3] 133 *.IN Encode1_S_i0.Dff_to_Enc1inv_[2] 134 *.IN Encode1_S_i0.Dff_to_Enc1inv_[1] 135 *.IN Encode1_S_i0.Dff_to_Enc1inv_[0] 136 *.OUT Encode1_S_i0.Enc1_to_Enc2_[62] 145 *.OUT Encode1_S_i0.Enc1_to_Enc2_[61] 146 *.OUT Encode1_S_i0.Enc1_to_Enc2_[60] 147 *.OUT Encode1_S_i0.Enc1_to_Enc2_[59] 148 *.OUT Encode1_S_i0.Enc1_to_Enc2_[58] 149 *.OUT Encode1_S_i0.Enc1_to_Enc2_[57] 150 *.OUT Encode1_S_i0.Enc1_to_Enc2_[56] 151 *.OUT Encode1_S_i0.Enc1_to_Enc2_[55] 152 *.OUT Encode1_S_i0.Enc1_to_Enc2_[54] 153 *.OUT Encode1_S_i0.Enc1_to_Enc2_[53] 154 *.OUT Encode1_S_i0.Enc1_to_Enc2_[52] 155 *.OUT Encode1_S_i0.Enc1_to_Enc2_[51] 156 *.OUT Encode1_S_i0.Enc1_to_Enc2_[50] 157 *.OUT Encode1_S_i0.Enc1_to_Enc2_[49] 158 *.OUT Encode1_S_i0.Enc1_to_Enc2_[48] 159 *.OUT Encode1_S_i0.Enc1_to_Enc2_[47] 160 *.OUT Encode1_S_i0.Enc1_to_Enc2_[46] 161 *.OUT Encode1_S_i0.Enc1_to_Enc2_[45] 162 *.OUT Encode1_S_i0.Enc1_to_Enc2_[44] 163 *.OUT Encode1_S_i0.Enc1_to_Enc2_[43] 164 *.OUT Encode1_S_i0.Enc1_to_Enc2_[42] 165 *.OUT Encode1_S_i0.Enc1_to_Enc2_[41] 166 *.OUT Encode1_S_i0.Enc1_to_Enc2_[40] 167 *.OUT Encode1_S_i0.Enc1_to_Enc2_[39] 168 *.OUT Encode1_S_i0.Enc1_to_Enc2_[38] 169 *.OUT Encode1_S_i0.Enc1_to_Enc2_[37] 170 *.OUT Encode1_S_i0.Enc1_to_Enc2_[36] 171 *.OUT Encode1_S_i0.Enc1_to_Enc2_[35] 172 *.OUT Encode1_S_i0.Enc1_to_Enc2_[34] 173 *.OUT Encode1_S_i0.Enc1_to_Enc2_[33] 174 *.OUT Encode1_S_i0.Enc1_to_Enc2_[32] 175 *.OUT Encode1_S_i0.Enc1_to_Enc2_[31] 176 *.OUT Encode1_S_i0.Enc1_to_Enc2_[30] 177 *.OUT Encode1_S_i0.Enc1_to_Enc2_[29] 178 *.OUT Encode1_S_i0.Enc1_to_Enc2_[28] 179 *.OUT Encode1_S_i0.Enc1_to_Enc2_[27] 180 *.OUT Encode1_S_i0.Enc1_to_Enc2_[26] 181 *.OUT Encode1_S_i0.Enc1_to_Enc2_[25] 182 *.OUT Encode1_S_i0.Enc1_to_Enc2_[24] 183 *.OUT Encode1_S_i0.Enc1_to_Enc2_[23] 184 *.OUT Encode1_S_i0.Enc1_to_Enc2_[22] 185 *.OUT Encode1_S_i0.Enc1_to_Enc2_[21] 186 *.OUT Encode1_S_i0.Enc1_to_Enc2_[20] 187 *.OUT Encode1_S_i0.Enc1_to_Enc2_[19] 188 *.OUT Encode1_S_i0.Enc1_to_Enc2_[18] 189 *.OUT Encode1_S_i0.Enc1_to_Enc2_[17] 190 *.OUT Encode1_S_i0.Enc1_to_Enc2_[16] 191 *.OUT Encode1_S_i0.Enc1_to_Enc2_[15] 192 *.OUT Encode1_S_i0.Enc1_to_Enc2_[14] 193 *.OUT Encode1_S_i0.Enc1_to_Enc2_[13] 194 *.OUT Encode1_S_i0.Enc1_to_Enc2_[12] 195 *.OUT Encode1_S_i0.Enc1_to_Enc2_[11] 196 *.OUT Encode1_S_i0.Enc1_to_Enc2_[10] 197 *.OUT Encode1_S_i0.Enc1_to_Enc2_[9] 198 *.OUT Encode1_S_i0.Enc1_to_Enc2_[8] 199 *.OUT Encode1_S_i0.Enc1_to_Enc2_[7] 200 *.OUT Encode1_S_i0.Enc1_to_Enc2_[6] 201 *.OUT Encode1_S_i0.Enc1_to_Enc2_[5] 202 *.OUT Encode1_S_i0.Enc1_to_Enc2_[4] 203 *.OUT Encode1_S_i0.Enc1_to_Enc2_[3] 204 *.OUT Encode1_S_i0.Enc1_to_Enc2_[2] 205 *.OUT Encode1_S_i0.Enc1_to_Enc2_[1] 206 *.OUT Encode1_S_i0.Enc1_to_Enc2_[0] 207 *.IN OutLatch_S_i0.D_in[5] 138 *.IN OutLatch_S_i0.D_in[4] 139 *.IN OutLatch_S_i0.D_in[3] 140 *.IN OutLatch_S_i0.D_in[2] 141 *.IN OutLatch_S_i0.D_in[1] 142 *.IN OutLatch_S_i0.D_in[0] 143 *.IN OutLatch_S_i0.HIT_5 65 *.OUT OutLatch_S_i0.Bit[5] 68 *.OUT OutLatch_S_i0.Bit[4] 69 *.OUT OutLatch_S_i0.Bit[3] 70 *.OUT OutLatch_S_i0.Bit[2] 71 *.OUT OutLatch_S_i0.Bit[1] 72 *.OUT OutLatch_S_i0.Bit[0] 73 *.OUT Ctrllogic_S_i0.Out0_5_6 138 *.OUT Ctrllogic_S_i0.Out0_4_6 139 *.OUT Ctrllogic_S_i0.Out0_3_6 140 *.OUT Ctrllogic_S_i0.Out0_2_6 141 *.OUT Ctrllogic_S_i0.Out0_1_6 142 *.OUT Ctrllogic_S_i0.Out0_0_6 143 *.OUT Ctrllogic_S_i0.MSB 138 *.IN Ctrllogic_S_i0.Phi_0 67 *.IN Ctrllogic_S_i0.DataStrobe_0 66 *.OUT Ctrllogic_S_i0.Hit_Out_5 65 *.OUT Ctrllogic_S_i0.DS_bar_7 144 *.IN tdc_Encode2_S_i0.in[62] 145 *.IN tdc_Encode2_S_i0.in[61] 146 *.IN tdc_Encode2_S_i0.in[60] 147 *.IN tdc_Encode2_S_i0.in[59] 148 *.IN tdc_Encode2_S_i0.in[58] 149 *.IN tdc_Encode2_S_i0.in[57] 150 *.IN tdc_Encode2_S_i0.in[56] 151 *.IN tdc_Encode2_S_i0.in[55] 152 *.IN tdc_Encode2_S_i0.in[54] 153 *.IN tdc_Encode2_S_i0.in[53] 154 *.IN tdc_Encode2_S_i0.in[52] 155 *.IN tdc_Encode2_S_i0.in[51] 156 *.IN tdc_Encode2_S_i0.in[50] 157 *.IN tdc_Encode2_S_i0.in[49] 158 *.IN tdc_Encode2_S_i0.in[48] 159 *.IN tdc_Encode2_S_i0.in[47] 160 *.IN tdc_Encode2_S_i0.in[46] 161 *.IN tdc_Encode2_S_i0.in[45] 162 *.IN tdc_Encode2_S_i0.in[44] 163 *.IN tdc_Encode2_S_i0.in[43] 164 *.IN tdc_Encode2_S_i0.in[42] 165 *.IN tdc_Encode2_S_i0.in[41] 166 *.IN tdc_Encode2_S_i0.in[40] 167 *.IN tdc_Encode2_S_i0.in[39] 168 *.IN tdc_Encode2_S_i0.in[38] 169 *.IN tdc_Encode2_S_i0.in[37] 170 *.IN tdc_Encode2_S_i0.in[36] 171 *.IN tdc_Encode2_S_i0.in[35] 172 *.IN tdc_Encode2_S_i0.in[34] 173 *.IN tdc_Encode2_S_i0.in[33] 174 *.IN tdc_Encode2_S_i0.in[32] 175 *.IN tdc_Encode2_S_i0.in[31] 176 *.IN tdc_Encode2_S_i0.in[30] 177 *.IN tdc_Encode2_S_i0.in[29] 178 *.IN tdc_Encode2_S_i0.in[28] 179 *.IN tdc_Encode2_S_i0.in[27] 180 *.IN tdc_Encode2_S_i0.in[26] 181 *.IN tdc_Encode2_S_i0.in[25] 182 *.IN tdc_Encode2_S_i0.in[24] 183 *.IN tdc_Encode2_S_i0.in[23] 184 *.IN tdc_Encode2_S_i0.in[22] 185 *.IN tdc_Encode2_S_i0.in[21] 186 *.IN tdc_Encode2_S_i0.in[20] 187 *.IN tdc_Encode2_S_i0.in[19] 188 *.IN tdc_Encode2_S_i0.in[18] 189 *.IN tdc_Encode2_S_i0.in[17] 190 *.IN tdc_Encode2_S_i0.in[16] 191 *.IN tdc_Encode2_S_i0.in[15] 192 *.IN tdc_Encode2_S_i0.in[14] 193 *.IN tdc_Encode2_S_i0.in[13] 194 *.IN tdc_Encode2_S_i0.in[12] 195 *.IN tdc_Encode2_S_i0.in[11] 196 *.IN tdc_Encode2_S_i0.in[10] 197 *.IN tdc_Encode2_S_i0.in[9] 198 *.IN tdc_Encode2_S_i0.in[8] 199 *.IN tdc_Encode2_S_i0.in[7] 200 *.IN tdc_Encode2_S_i0.in[6] 201 *.IN tdc_Encode2_S_i0.in[5] 202 *.IN tdc_Encode2_S_i0.in[4] 203 *.IN tdc_Encode2_S_i0.in[3] 204 *.IN tdc_Encode2_S_i0.in[2] 205 *.IN tdc_Encode2_S_i0.in[1] 206 *.IN tdc_Encode2_S_i0.in[0] 207 *.OUT tdc_Encode2_S_i0.out[5] 138 *.OUT tdc_Encode2_S_i0.out[4] 139 *.OUT tdc_Encode2_S_i0.out[3] 140 *.OUT tdc_Encode2_S_i0.out[2] 141 *.OUT tdc_Encode2_S_i0.out[1] 142 *.OUT tdc_Encode2_S_i0.out[0] 143 *.Vnwell 1688 0 5 *.Vbulk 1687 0 0 *.Vpwell 1689 0 0 *.Vbulk 1687 0 5 *TEXT D_in_[63] " "; *TEXT HIT_5 " "; *TEXT DataStrobe_0 " "; *TEXT Phi_0 " "; *TEXT Bit_[5] " "; *TEXT node0[63] " "; *TEXT w0.[1][3] "62:0"; *TEXT w1.[1][0] "63:1"; *TEXT node1[5] " "; *TEXT w2.[1][0] "0"; *TEXT w3.[1][0] "1"; *TEXT w4.[1][0] "2"; *TEXT w5.[1][0] "3"; *TEXT w6.[1][0] "4"; *TEXT w7.[1][0] "5"; *TEXT "ChannelR"; .ENDS ChannelR_S * start main CELL TDC64x8_S XDelayBuffer_S_i0 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 + 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 + 187 188 189 190 191 192 193 194 195 196 197 68 69 70 71 72 73 74 75 76 77 78 + 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 + 123 124 125 126 127 128 129 130 131 198 18 199 132 17 67 133 14303 14304 + DelayBuffer_S XChannel_S_i0 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 + 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 + 188 189 190 191 192 193 194 195 196 197 8 16 198 19 20 21 22 23 24 14303 14304 + Channel_S XChannelR_S_i0 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 + 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 + 188 189 190 191 192 193 194 195 196 197 7 15 198 25 26 27 28 29 30 14303 14304 + ChannelR_S XChannel_S_i1 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 + 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 + 188 189 190 191 192 193 194 195 196 197 6 14 198 31 32 33 34 35 36 14303 14304 + Channel_S XChannelR_S_i2 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 + 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 + 188 189 190 191 192 193 194 195 196 197 5 13 198 37 38 39 40 41 42 14303 14304 + ChannelR_S XChannel_S_i2 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 + 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 + 188 189 190 191 192 193 194 195 196 197 4 12 198 43 44 45 46 47 48 14303 14304 + Channel_S XChannelR_S_i3 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 + 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 + 188 189 190 191 192 193 194 195 196 197 3 11 198 49 50 51 52 53 54 14303 14304 + ChannelR_S XChannel_S_i4 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 + 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 + 188 189 190 191 192 193 194 195 196 197 2 10 198 55 56 57 58 59 60 14303 14304 + Channel_S XChannelR_S_i5 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 + 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 + 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 + 188 189 190 191 192 193 194 195 196 197 1 9 198 61 62 63 64 65 66 14303 14304 + ChannelR_S *.OUT hit[7] 1 *.OUT hit[6] 2 *.OUT hit[5] 3 *.OUT hit[4] 4 *.OUT hit[3] 5 *.OUT hit[2] 6 *.OUT hit[1] 7 *.OUT hit[0] 8 *.IN DataStrobe[7] 9 *.IN DataStrobe[6] 10 *.IN DataStrobe[5] 11 *.IN DataStrobe[4] 12 *.IN DataStrobe[3] 13 *.IN DataStrobe[2] 14 *.IN DataStrobe[1] 15 *.IN DataStrobe[0] 16 *.IN RESET 17 *.IN PHI_in 18 *.OUT tdc_out0[5] 19 *.OUT tdc_out0[4] 20 *.OUT tdc_out0[3] 21 *.OUT tdc_out0[2] 22 *.OUT tdc_out0[1] 23 *.OUT tdc_out0[0] 24 *.OUT tdc_out1[5] 25 *.OUT tdc_out1[4] 26 *.OUT tdc_out1[3] 27 *.OUT tdc_out1[2] 28 *.OUT tdc_out1[1] 29 *.OUT tdc_out1[0] 30 *.OUT tdc_out2[5] 31 *.OUT tdc_out2[4] 32 *.OUT tdc_out2[3] 33 *.OUT tdc_out2[2] 34 *.OUT tdc_out2[1] 35 *.OUT tdc_out2[0] 36 *.OUT tdc_out3[5] 37 *.OUT tdc_out3[4] 38 *.OUT tdc_out3[3] 39 *.OUT tdc_out3[2] 40 *.OUT tdc_out3[1] 41 *.OUT tdc_out3[0] 42 *.OUT tdc_out4[5] 43 *.OUT tdc_out4[4] 44 *.OUT tdc_out4[3] 45 *.OUT tdc_out4[2] 46 *.OUT tdc_out4[1] 47 *.OUT tdc_out4[0] 48 *.OUT tdc_out5[5] 49 *.OUT tdc_out5[4] 50 *.OUT tdc_out5[3] 51 *.OUT tdc_out5[2] 52 *.OUT tdc_out5[1] 53 *.OUT tdc_out5[0] 54 *.OUT tdc_out6[5] 55 *.OUT tdc_out6[4] 56 *.OUT tdc_out6[3] 57 *.OUT tdc_out6[2] 58 *.OUT tdc_out6[1] 59 *.OUT tdc_out6[0] 60 *.OUT tdc_out7[5] 61 *.OUT tdc_out7[4] 62 *.OUT tdc_out7[3] 63 *.OUT tdc_out7[2] 64 *.OUT tdc_out7[1] 65 *.OUT tdc_out7[0] 66 *.OUT vcap 67 *.OUT TDC_taps[63] 68 *.OUT TDC_taps[62] 69 *.OUT TDC_taps[61] 70 *.OUT TDC_taps[60] 71 *.OUT TDC_taps[59] 72 *.OUT TDC_taps[58] 73 *.OUT TDC_taps[57] 74 *.OUT TDC_taps[56] 75 *.OUT TDC_taps[55] 76 *.OUT TDC_taps[54] 77 *.OUT TDC_taps[53] 78 *.OUT TDC_taps[52] 79 *.OUT TDC_taps[51] 80 *.OUT TDC_taps[50] 81 *.OUT TDC_taps[49] 82 *.OUT TDC_taps[48] 83 *.OUT TDC_taps[47] 84 *.OUT TDC_taps[46] 85 *.OUT TDC_taps[45] 86 *.OUT TDC_taps[44] 87 *.OUT TDC_taps[43] 88 *.OUT TDC_taps[42] 89 *.OUT TDC_taps[41] 90 *.OUT TDC_taps[40] 91 *.OUT TDC_taps[39] 92 *.OUT TDC_taps[38] 93 *.OUT TDC_taps[37] 94 *.OUT TDC_taps[36] 95 *.OUT TDC_taps[35] 96 *.OUT TDC_taps[34] 97 *.OUT TDC_taps[33] 98 *.OUT TDC_taps[32] 99 *.OUT TDC_taps[31] 100 *.OUT TDC_taps[30] 101 *.OUT TDC_taps[29] 102 *.OUT TDC_taps[28] 103 *.OUT TDC_taps[27] 104 *.OUT TDC_taps[26] 105 *.OUT TDC_taps[25] 106 *.OUT TDC_taps[24] 107 *.OUT TDC_taps[23] 108 *.OUT TDC_taps[22] 109 *.OUT TDC_taps[21] 110 *.OUT TDC_taps[20] 111 *.OUT TDC_taps[19] 112 *.OUT TDC_taps[18] 113 *.OUT TDC_taps[17] 114 *.OUT TDC_taps[16] 115 *.OUT TDC_taps[15] 116 *.OUT TDC_taps[14] 117 *.OUT TDC_taps[13] 118 *.OUT TDC_taps[12] 119 *.OUT TDC_taps[11] 120 *.OUT TDC_taps[10] 121 *.OUT TDC_taps[9] 122 *.OUT TDC_taps[8] 123 *.OUT TDC_taps[7] 124 *.OUT TDC_taps[6] 125 *.OUT TDC_taps[5] 126 *.OUT TDC_taps[4] 127 *.OUT TDC_taps[3] 128 *.OUT TDC_taps[2] 129 *.OUT TDC_taps[1] 130 *.OUT TDC_taps[0] 131 *.OUT Phase_B 132 *.OUT Phase_A 133 *.OUT DelayBuffer_S_i0.Out_to_Dff[63] 134 *.OUT DelayBuffer_S_i0.Out_to_Dff[62] 135 *.OUT DelayBuffer_S_i0.Out_to_Dff[61] 136 *.OUT DelayBuffer_S_i0.Out_to_Dff[60] 137 *.OUT DelayBuffer_S_i0.Out_to_Dff[59] 138 *.OUT DelayBuffer_S_i0.Out_to_Dff[58] 139 *.OUT DelayBuffer_S_i0.Out_to_Dff[57] 140 *.OUT DelayBuffer_S_i0.Out_to_Dff[56] 141 *.OUT DelayBuffer_S_i0.Out_to_Dff[55] 142 *.OUT DelayBuffer_S_i0.Out_to_Dff[54] 143 *.OUT DelayBuffer_S_i0.Out_to_Dff[53] 144 *.OUT DelayBuffer_S_i0.Out_to_Dff[52] 145 *.OUT DelayBuffer_S_i0.Out_to_Dff[51] 146 *.OUT DelayBuffer_S_i0.Out_to_Dff[50] 147 *.OUT DelayBuffer_S_i0.Out_to_Dff[49] 148 *.OUT DelayBuffer_S_i0.Out_to_Dff[48] 149 *.OUT DelayBuffer_S_i0.Out_to_Dff[47] 150 *.OUT DelayBuffer_S_i0.Out_to_Dff[46] 151 *.OUT DelayBuffer_S_i0.Out_to_Dff[45] 152 *.OUT DelayBuffer_S_i0.Out_to_Dff[44] 153 *.OUT DelayBuffer_S_i0.Out_to_Dff[43] 154 *.OUT DelayBuffer_S_i0.Out_to_Dff[42] 155 *.OUT DelayBuffer_S_i0.Out_to_Dff[41] 156 *.OUT DelayBuffer_S_i0.Out_to_Dff[40] 157 *.OUT DelayBuffer_S_i0.Out_to_Dff[39] 158 *.OUT DelayBuffer_S_i0.Out_to_Dff[38] 159 *.OUT DelayBuffer_S_i0.Out_to_Dff[37] 160 *.OUT DelayBuffer_S_i0.Out_to_Dff[36] 161 *.OUT DelayBuffer_S_i0.Out_to_Dff[35] 162 *.OUT DelayBuffer_S_i0.Out_to_Dff[34] 163 *.OUT DelayBuffer_S_i0.Out_to_Dff[33] 164 *.OUT DelayBuffer_S_i0.Out_to_Dff[32] 165 *.OUT DelayBuffer_S_i0.Out_to_Dff[31] 166 *.OUT DelayBuffer_S_i0.Out_to_Dff[30] 167 *.OUT DelayBuffer_S_i0.Out_to_Dff[29] 168 *.OUT DelayBuffer_S_i0.Out_to_Dff[28] 169 *.OUT DelayBuffer_S_i0.Out_to_Dff[27] 170 *.OUT DelayBuffer_S_i0.Out_to_Dff[26] 171 *.OUT DelayBuffer_S_i0.Out_to_Dff[25] 172 *.OUT DelayBuffer_S_i0.Out_to_Dff[24] 173 *.OUT DelayBuffer_S_i0.Out_to_Dff[23] 174 *.OUT DelayBuffer_S_i0.Out_to_Dff[22] 175 *.OUT DelayBuffer_S_i0.Out_to_Dff[21] 176 *.OUT DelayBuffer_S_i0.Out_to_Dff[20] 177 *.OUT DelayBuffer_S_i0.Out_to_Dff[19] 178 *.OUT DelayBuffer_S_i0.Out_to_Dff[18] 179 *.OUT DelayBuffer_S_i0.Out_to_Dff[17] 180 *.OUT DelayBuffer_S_i0.Out_to_Dff[16] 181 *.OUT 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