84 ELEFANT preproduction chips have been characterized in some detail. On 11 chips, one or more channels were unresponsive or of unacceptable quality. The following figures show results on over 650 working channels Unless noted otherwise, settings common to all measurements are: *) AVDD, DVDD = 5.0V *) sys_clock frequency = 64.00MHz *) Gain setting = minimum gain (x11) *) Vtop=4.00V, Vbot=1.00V, Vmid=not connected *) About 1000 data points are used to cover the FADC and TDC range. All fadc-related quantities are input voltage referred. ***************************************************************** FADC and TDC performance, a single channel ***************************************************************** 1) fadc_4V7.ps A typical fadc and tdc channel fadc_5V1.ps tdc_4V7.ps tdc_5V1.ps Plot of typical fadc and tdc performance measured at 60MHz and VDD=4.7V and 5.1V. FADC-graphs: top chart: FADC response to input voltage and least squares straight line fit. middle chart: FADC count deviation from ideal FADC with equal-width bins. bottom chart: FADC binwidths, measured in multiples of 0.245mV input voltage. TDC-graphs: top chart: TDC response to input pulse delay and least squares straight line fit. middle chart: TDC count deviation from ideal TDC with equal-width bins. bottom chart: TDC binwidths, measured in multiples of 70ps. --------------------------------------------------------------- 2) tdc_frequency.ps: TDC performance at various frequencies On all three charts: trace 1) 70MHz trace 2) 60MHz trace 3) 50MHz top chart: TDC response vs input pulse delay middle chart: TDC deviation from ideal TDC with equal-width bins. Traces 1) and 2) have 6 and 3 counts added to them, respectively. bottom chart: TDC binwidths, measured in multiples of 20ps. Traces 1) and 2) have 2ns and 1ns added to them, respectively. ***************************************************************** FADC and TDC performance, statistics plots ***************************************************************** Statistics plot contain data obtained on 84*8=672 channels. Non-functional channels have not been excluded from the plots, but show up with out of range results, zero or infinity. They therefore do not contribute to the histograms. 1) fadc_slope.ps: FADC-slope upper chart: Plot of FADC-slopes vs channel number, bad channels included. lower chart: Histogram of above plot, Width of histogram bin: 0.001 count/mV ----------------------------------------------------------------- 2) fadc_zero.ps: Input voltage offset upper chart: Plot of input voltage offset vs channel number, bad channels included. lower chart: Histogram of above plot, Width of histogram bin: 1mV ----------------------------------------------------------------- 3) tdc_slope.ps: TDC-slope upper chart: Plot of vs TDC-slope channel number, bad channels included. lower chart: Histogram of above plot, Width of histogram bin: 0.0003 count/ns Note: Since the TDC-slope is determined by the sample clock width, this is essentially a measurements of the relative frequency stability of the two pulsers in use, and statistics noise from the data analysis. ------------------------------------------------------------------ 4) tdc_zero.ps: TDC-zero upper chart: Plot of time zero vs channel number, bad channels included. lower chart: Histogram of above plot, Width of histogram bin: 50ps Note: The absolute value of time zero is an uninteresting quntity. It is determined by the cable length and the time since the last synch pulse. ------------------------------------------------------------------- 5) dnl.ps: ADC bin widths upper chart: Histogram of FADC bin widths, bad channels excluded. Width of histogram bin: 0.25mV lower chart: Histogram of TDC bin widths, bad channels excluded. Width of histogram bin: 70ps ------------------------------------------------------------------- 6) finl.ps: FADC integral nonlinearity upper chart: Histogram of FADC deviations from ideal FADC, bad channels excluded. Width of histogram bin: 1 count lower chart: As above, but on logarithmic scale. -------------------------------------------------------------------- 7) tinl.ps: TDC integral nonlinearity upper chart: Histogram of TDC deviations from ideal TDC, bad channels excluded. Width of histogram bin: 1 count lower chart: As above, but on logarithmic scale. --------------------------------------------------------------------- 8) fadc_rms.ps: rms deviation of the FADC's from the ideal. The quantity computed for each channel is the standard deviation of the count difference between real and ideal FADC. Ideally that number would be zero. upper chart: FADC rms error in counts, bad channels included. lower chart: Histogram of the above. Width of histogram bin: 0.025 counts --------------------------------------------------------------------- 9) tdc_rms.ps: rms deviation of the TDC's from the ideal. The quantity computed for each channel is the standard deviation of the count difference between real and ideal TDC. Ideally that number would be zero. upper chart: TDC rms error in counts, bad channels included. lower chart: Histogram of the above. Width of histogram bin: 0.0125 counts ***************************************************************** Plots concerning the offset problem ***************************************************************** 1) vref.ps: FADC response vs Vref Measurements taken at 50MHz and 60MHz. Note that the 50MHz trace has been shifted downward by 10 counts. Without the shift the two traces fall on top of each other. ----------------------------------------------------------------- 2) offset_resistor.ps Effect of series resistor Effect of a series resistor between the FADC and the analog receiver output, measured at 50MHz. trace 1) No resistor trace 2) R=1.5kOhm trace 3) R=3.0kOhm Note, that the resistors have been realized as ion-beam deposited tungsten traces on the IC. No external components were used. ***************************************************************** A Plot concerning the code error problem ***************************************************************** 1) fadc_frequency.ps Three consecutive measurements of FADC output vs input voltage at different frequencies. Top, middle, and bottom trace were taken at 70MHz, 60MHz, and 50MHz, respectively. The traces have been offset by 20 counts (top trace) and 10 counts (middle trace). ***************************************************************** A Plot concerning the PLL control voltage ***************************************************************** 1) PLL_hist.ps Histogram of the delayed locked loop control voltage at 60MHz, measured on 50 IC's. Width of histogram bin: 0.050V